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FDC37C672 Enhanced Super I/O Controller with Fast IR
Datasheet
Product Features
5 Volt Operation PC98/99 and ACPI 1.0 Compliant ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management
- Shadowed Write-Only Registers for ACPI Compliance
Serial Ports
- Two Full Function Serial Ports - High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry - 480 Address and Eight IRQ Options
System Management Interrupt, Watchdog Timer 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Supports Two Floppy Drives Directly - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16-Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - 480 Address, Up to Eight IRQ and Three DMA Options
Infrared Port
- - - - - - - Multiprotocol Infrared Interface 128-Byte Data FIFO IrDA 1.1 Compliant TEMIC/HP Module Support Consumer IR SHARP ASK IR 480 Address, Up to Eight IRQ and Three DMA Options
Multi-Mode Parallel Port with ChiProtect
- Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - IEEE 1284 Compliant Enhanced Capabilities Port (ECP) - ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 480 Address, Up to Eight IRQ and Three DMA Options
Floppy Disk Available on Parallel Port Pins Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes
ISA Host Interface
- - - - - - 16-Bit Address Qualification 8-Bit Data Bus IOCHRDY for ECP and Fast IR Three 8-Bit DMA Channels Eight Direct Parallel IRQs Serial IRQ Option Compatible with Serialized IRQ Support for PCI Systems
Keyboard Controller
- - - - - - - - - - 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8-Bit Counter Timer Port 92 Support 8042 P12 and P16 Outputs
100 Pin QFP and TQFP Packages
SMSC FDC37C672
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Rev. 10-29-03
DATASHEET
Enhanced Super I/O Controller with Fast IR Datasheet
ORDERING INFORMATION
Order Number(s): FDC37C672QFP for 100 pin QFP package FDC37C672TQFP for 100 pin TQFP package
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC FDC37C672
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Rev. 10-29-03
DATASHEET
Enhanced Super I/O Controller with Fast IR Datasheet
FDC37C672 Datasheet Revision History
REVISION LEVEL AND DATE Rev. 10-29-03 Rev. 10-28-03 Rev. 10-28-03 Rev. 10-27-03 Rev. 10-27-03 Rev. 10-27-03 Rev. 06-09-97 Rev. 06-09-97 Rev. 06-09-97 Rev. 06-09-97 SECTION/FIGURE/ENTRY Ordering Information, page 2 Chapter 3 - Description of Pin Functions, page 12 Chapter 4 - Description of Multifunction Pins, page 15 Figure 2.2 - FDC37C672 100 Pin TQFP, page 11 Figure 23.2 - 100 Pin TQFP Package Outline, 14X14X1.4 Body, 2 MM Footprint, page 173 Features - Cover Figure 2.1 - FDC37C672 100 Pin QFP, page 10 Section 6.1.4 - Tape Drive Register (TDR), page 24 Table 6.3 - Tape Select Bits, page 24 Table 19.1 - Configuration Registers, page 123 CORRECTION Update order numbers for QFP and TQFP packages. Added TQFP values. Added TQFP values. Added TQFP pin layout. Added TQFP package outline. Added TQFP package. Pin #90 added to Pin-Out. Updated section. Updated table. Updated table.
SMSC FDC37C672
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PRELIMINARY DATASHEET
Enhanced Super I/O Controller with Fast IR Datasheet
Table of Contents
FDC37C672 Datasheet Revision History .................................................................................................. 3
Chapter 1 Chapter 2 Chapter 3
3.1
General Description................................................................................................................ 9 Pin Configuration.................................................................................................................. 10 Description of Pin Functions ................................................................................................ 12
Buffer Type Descriptions ............................................................................................................................14
Chapter 4 Chapter 5
5.1 5.2
Description of Multifunction Pins .......................................................................................... 15 Functional Description.......................................................................................................... 17
Super I/O Registers....................................................................................................................................17 Host Processor Interface............................................................................................................................17
Chapter 6
Floppy Disk Controller .......................................................................................................... 18
6.1 FDC Internal Registers...............................................................................................................................18 6.1.1 Status Register A (SRA) .....................................................................................................................19 6.1.2 Status Register B (SRB) .....................................................................................................................21 6.1.3 Digital Output Register (DOR).............................................................................................................23 6.1.4 Tape Drive Register (TDR) .................................................................................................................24 6.1.5 Data Rate Select Register (DSR)........................................................................................................26 6.1.6 Main Status Register...........................................................................................................................29 6.1.7 Data Register (FIFO)...........................................................................................................................29 6.1.8 Digital Input Register (DIR) .................................................................................................................31 6.1.9 Configuration Control Register (CCR).................................................................................................33 6.1.10 Status Register Encoding ................................................................................................................34 6.2 RESET .......................................................................................................................................................36 6.2.1 RESET Pin (Hardware Reset).............................................................................................................36 6.2.2 DOR Reset vs. DSR Reset (Software Reset) .....................................................................................36 6.3 Modes of Operation....................................................................................................................................36 6.3.1 PC/AT mode - (IDENT high, MFM a "don't care") ...............................................................................36 6.3.2 PS/2 mode - (IDENT low, MFM high)..................................................................................................36 6.3.3 Model 30 mode - (IDENT low, MFM low) ............................................................................................36 6.4 DMA Transfers ...........................................................................................................................................37 6.5 Controller Phases.......................................................................................................................................37 6.5.1 Command Phase ................................................................................................................................37 6.5.2 Execution Phase .................................................................................................................................37 6.5.3 Data Transfer Termination ..................................................................................................................38 6.5.4 Result Phase.......................................................................................................................................39
Chapter 7 Chapter 8
Command Set/Descriptions ................................................................................................. 40 Instruction Set ...................................................................................................................... 43
8.1 Data Transfer Commands ..........................................................................................................................49 8.1.1 Read Data ...........................................................................................................................................49 8.1.2 Read Deleted Data..............................................................................................................................51 8.1.3 Read A Track ......................................................................................................................................51 8.1.4 Write Data ...........................................................................................................................................52 8.1.5 Write Deleted Data..............................................................................................................................53 8.1.6 Verify...................................................................................................................................................53 8.1.7 Format A Track ...................................................................................................................................54 8.2 Control Commands ....................................................................................................................................55 8.2.1 Read ID...............................................................................................................................................55 8.2.2 Recalibrate ..........................................................................................................................................55 8.2.3 Seek....................................................................................................................................................56 8.2.4 Sense Interrupt Status ........................................................................................................................56 8.2.5 Sense Drive Status .............................................................................................................................57 8.2.6 Specify ................................................................................................................................................57 8.2.7 Configure ............................................................................................................................................58 8.2.8 Version................................................................................................................................................59 8.2.9 Relative Seek ......................................................................................................................................59 8.2.10 Perpendicular Mode ........................................................................................................................60 8.3 LOCK .........................................................................................................................................................61
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8.4 8.5
Enhanced DUMPREG................................................................................................................................61 Compatibility...............................................................................................................................................62
Chapter 9
Serial Port (UART) ............................................................................................................... 63
9.1 Register Description ...................................................................................................................................63 9.1.1 Receive Buffer Register (RB) ..............................................................................................................64 9.1.2 Transmit Buffer Register (TB) .............................................................................................................64 9.1.3 Interrupt Enable Register (IER) ...........................................................................................................64 9.1.4 FIFO Control Register (FCR) ..............................................................................................................65 9.1.5 Interrupt Identification Register (IIR) ...................................................................................................65 9.1.6 Line Control Register (LCR) ................................................................................................................67 9.1.7 Modem Control Register (MCR)..........................................................................................................68 9.1.8 Line Status Register (LSR) .................................................................................................................69 9.1.9 Modem Status Register (MSR) ...........................................................................................................71 9.1.10 Scratchpad Register (SCR) .............................................................................................................72 9.2 Programmable Baud Rate Generator (and Divisor Latches DLH, DLL) .....................................................72 9.2.1 Effect Of The Reset on Register File...................................................................................................72 9.3 FIFO Interrupt Mode Operation ..................................................................................................................72 9.4 FIFO Polled Mode Operation .....................................................................................................................73 9.5 Notes on Serial Port Operation ..................................................................................................................76 9.5.1 FIFO Mode Operation: ........................................................................................................................76
Chapter 10 Chapter 11 Chapter 12
Infrared Interface .................................................................................................................. 78 Fast IR .................................................................................................................................. 79 Parallel Port.......................................................................................................................... 80
12.1 IBM XT/AT Compatible, Bi-Directional and EPP Modes .........................................................................81 12.2 Extended Capabilities Parallel Port.........................................................................................................87 12.2.1 Vocabulary.......................................................................................................................................87 12.3 ISA Implementation Standard.................................................................................................................88 12.3.1 Register Definitions .........................................................................................................................90 12.4 Operation................................................................................................................................................96 12.4.1 Mode Switching/Software Control....................................................................................................96 12.4.2 Data Compression...........................................................................................................................97 12.4.3 Pin Definition ...................................................................................................................................97 12.4.4 ISA Connections..............................................................................................................................97 12.4.5 Interrupts .........................................................................................................................................98 12.4.6 FIFO Operation................................................................................................................................98 12.5 DMA Transfers........................................................................................................................................98 12.5.1 Programmed I/O Mode or Non-DMA Mode .....................................................................................99 12.5.2 Programmed I/O - Transfers from the FIFO to the Host ..................................................................99 12.5.3 Programmed I/O - Transfers from the Host to the FIFO ................................................................100 12.6 Parallel Port Floppy Disk Controller ......................................................................................................100
Chapter 13 Chapter 14
Auto Power Management................................................................................................... 102 Serial IRQ........................................................................................................................... 106
14.1 Serial Interrupts ....................................................................................................................................106 14.1.1 Timing Diagrams For IRQSER Cycle ............................................................................................106 14.1.2 IRQSER Cycle Control ..................................................................................................................107 14.1.3 IRQSER Data Frame.....................................................................................................................108 14.1.4 Stop Cycle Control.........................................................................................................................108 14.1.5 Latency ..........................................................................................................................................109 14.1.6 EOI/ISR Read Latency ..................................................................................................................109 14.1.7 AC/DC Specification Issue ............................................................................................................109 14.1.8 Reset and Initialization ..................................................................................................................109
Chapter 15 Chapter 16 Chapter 17
GP Index Registers ............................................................................................................ 110 Watch Dog Timer ............................................................................................................... 111 8042 Keyboard Controller Description ............................................................................... 112
17.1 Keyboard ISA Interface.........................................................................................................................112 17.1.1 Keyboard Data Write .....................................................................................................................113 17.1.2 Keyboard Data Read .....................................................................................................................113 17.1.3 Keyboard Command Write ............................................................................................................113 17.1.4 Keyboard Status Read ..................................................................................................................113
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17.1.5 CPU-to-Host Communication ........................................................................................................113 17.1.6 Host-to-CPU Communication ........................................................................................................113 17.1.7 KIRQ..............................................................................................................................................114 17.1.8 MIRQ .............................................................................................................................................114 17.1.9 Gate A20 .......................................................................................................................................114 17.2 External Keyboard and Mouse Interface...............................................................................................114 17.3 Keyboard Power Management .............................................................................................................114 17.3.1 Soft Power Down Mode.................................................................................................................114 17.3.2 Hard Power Down Mode ...............................................................................................................115 17.4 Interrupts ..............................................................................................................................................115 17.5 Memory Configurations.........................................................................................................................115 17.5.1 Register Definitions .......................................................................................................................115 17.5.2 Status Register ..............................................................................................................................115 17.6 External Clock Signal............................................................................................................................116 17.7 Default Reset Conditions ......................................................................................................................116 17.8 GATEA20 and Keyboard Reset ............................................................................................................116 17.9 Port 92 Fast GATEA20 and Keyboard Reset .......................................................................................117 17.9.1 Port 92 Register.............................................................................................................................117 17.9.2 8042 P12 and P16 Functions ........................................................................................................118
Chapter 18
System Management Interrupt (SMI) ................................................................................. 120
18.1 Registers ..............................................................................................................................................120 18.1.1 SMI Enable Registers....................................................................................................................120 18.1.2 SMI Status Registers.....................................................................................................................120
Chapter 19
Configuration ...................................................................................................................... 121
19.1 System Elements..................................................................................................................................121 19.1.1 Primary Configuration Address Decoder .......................................................................................121 19.1.2 Entering the Configuration State....................................................................................................121 19.1.3 Exiting the Configuration State ......................................................................................................122 19.2 Configuration Sequence .......................................................................................................................122 19.2.1 Enter Configuration Mode..............................................................................................................122 19.2.2 Configuration Mode .......................................................................................................................122 19.2.3 Exit Configuration Mode ................................................................................................................122 19.2.4 Programming Example ..................................................................................................................123 19.2.5 Chip Level (Global) Control/Configuration Registers [0x00-0x2F] .................................................125 19.2.6 Logical Device Configuration/Control Registers [0x30-0xFF] ........................................................128 19.2.7 Note A. Logical Device IRQ and DMA Operation ..........................................................................132 19.2.8 SMSC Defined Logical Device Configuration Registers ................................................................132
Chapter 20
20.1 20.2
Operational Description...................................................................................................... 143
Maximum Guaranteed Ratings*............................................................................................................143 DC Electrical Characteristics ................................................................................................................143
Chapter 21 Chapter 22 Chapter 23
Timing Diagrams ................................................................................................................146 ECP Parallel Port Timing.................................................................................................... 164 Package Outlines ...............................................................................................................172
List of Figures
Figure 2.1 - FDC37C672 100 Pin QFP ........................................................................................................................10 Figure 2.2 - FDC37C672 100 Pin TQFP ......................................................................................................................11 Figure 4.1 - FDC37C672 Block Diagram......................................................................................................................16 Figure 11.1 - IR Interface Block Diagram .....................................................................................................................79 Figure 17.1 - Keyboard and Mouse Interface.............................................................................................................112 Figure 17.2 - Gate A20 Turn-On Sequence Timing....................................................................................................119 Figure 21.1 - IOW Timing for Port 92 .........................................................................................................................147 Figure 21.2 - Power-Up Timing ..................................................................................................................................147 Figure 21.3 - ISA Write...............................................................................................................................................148 Figure 21.4 - ISA Read ..............................................................................................................................................149 Figure 21.5 - Internal 8042 CPU Timing.....................................................................................................................150 Figure 21.6 - Input Clock Timing ................................................................................................................................151
SMSC FDC37C672
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Enhanced Super I/O Controller with Fast IR Datasheet
Figure 21.7 - Reset Timing.........................................................................................................................................151 Figure 21.8 - DMA Timing (Single Transfer Mode).....................................................................................................152 Figure 21.9 - DMA Timing (Burst Transfer Mode) ......................................................................................................153 Figure 21.10 - Disk Drive Timing (At Mode Only).......................................................................................................154 Figure 21.11 - Serial Port Timing ...............................................................................................................................155 Figure 21.12 - Parallel Port Timing.............................................................................................................................156 Figure 21.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................157 Figure 21.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................159 Figure 21.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................161 Figure 21.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................163 Figure 22.1 - Parallel Port FIFO Timing.......................................................................................................................165 Figure 22.2 - ECP Parallel Port Forward Timing..........................................................................................................166 Figure 22.3 - ECP Parallel Port Reverse Timing .........................................................................................................167 Figure 22.4 - IrDA Receive Timing .............................................................................................................................168 Figure 22.5 - IrDA Transmit Timing ............................................................................................................................169 Figure 22.6 - Amplitude Shift Keyed IR Receive Timing ............................................................................................170 Figure 22.7 - Amplitude Shift Keyed IR Transmit Timing ...........................................................................................171 Figure 23.1 - 100 Pin QFP Package Outline and Parameters .....................................................................................172 Figure 23.2 - 100 Pin TQFP Package Outline, 14X14X1.4 Body, 2 MM Footprint .......................................................173
List of Tables
Table 5.1 - Super I/O Block Addresses .........................................................................................................................17 Table 6.1 - Status, Data and Control Registers .............................................................................................................18 Table 6.2 - Drive Activation Values ...............................................................................................................................24 Table 6.3 - Tape Select Bits..........................................................................................................................................24 Table 6.4 - Internal 2 Drive Decode - Normal ................................................................................................................24 Table 6.5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped .....................................................................................25 Table 6.6 - Media ID1...................................................................................................................................................26 Table 6.7 - Media ID0...................................................................................................................................................26 Table 6.8 - Drive Type ID..............................................................................................................................................26 Table 6.9 - Precompensation Delays ............................................................................................................................27 Table 6.10 - Data Rates ...............................................................................................................................................28 Table 6.11 - DRVDEN Mapping....................................................................................................................................28 Table 6.12 - Default Precompensation Delays ..............................................................................................................28 Table 6.14 - FIFO Service Delay ....................................................................................................................................30 Table 6.15 - Status Register 0 ......................................................................................................................................34 Table 6.16 - Status Register 1 ......................................................................................................................................34 Table 6.17 - Status Register 2 ......................................................................................................................................35 Table 6.18 - Status Register 3 ......................................................................................................................................35 Table 7.1 - Description of Command Symbols ..............................................................................................................40 Table 8.1 - Sector Sizes ...............................................................................................................................................50 Table 8.2 - Effects of MT and N Bits .............................................................................................................................50 Table 8.3 - Skip Bit vs Read Data Command ................................................................................................................51 Table 8.4 - Skip Bit vs. Read Deleted Data Command ..................................................................................................51 Table 8.5 - Result Phase Table.....................................................................................................................................52 Table 8.6 - Verify Command Result Phase Table..........................................................................................................53 Table 8.7 - Format Fields..............................................................................................................................................54 Table 8.8 - Typical Values for Formatting......................................................................................................................55 Table 8.9 - Interrupt Identification..................................................................................................................................57 Table 8.10 - Drive Control Delays (ms) .........................................................................................................................58 Table 8.11 - Effects of WGATE and GAP Bits...............................................................................................................61 Table 9.1 - Addressing the Serial Port...........................................................................................................................63 Table 9.2 - Interrupt Control Table ................................................................................................................................67 Table 9.3 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k..........................................................................................73 Table 9.4 - Reset Function Table..................................................................................................................................74 Table 9.5 - Register Summary for an Individual UART Channel ..................................................................................75 Table 11.1 - DRVDEN1 MUXING.................................................................................................................................79
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Enhanced Super I/O Controller with Fast IR Datasheet
Table 12.1 - Parallel Port Connector .............................................................................................................................81 Table 12.2 - EPP Pin Descriptions ................................................................................................................................86 Table 12.3 - ECP Pin Descriptions................................................................................................................................89 Table 12.4 - ECP Register Definitions...........................................................................................................................90 Table 12.5 - Mode Descriptions ....................................................................................................................................90 Table 12.6A - Extended Control Register......................................................................................................................95 Table 12.7 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) .................97 Table 12.8 - FDC Parallel Port Pins ............................................................................................................................101 Table 13.1 - PC/AT and PS/2 Available Registers.......................................................................................................103 Table 13.2 - State of System Pins in Auto Powerdown................................................................................................104 Table 13.3 - State of Floppy Disk Drive Interface Pins in Powerdown..........................................................................104 Table 14.1 - IRQSER Sampling Periods ....................................................................................................................108 Table 15.1 - GP Index and Data Register ...................................................................................................................110 Table 15.2- Index and Data Register Normal (Run) Mode...........................................................................................110 Table 17.1 - ISA I/O Address Map ..............................................................................................................................113 Table 17.2 - Host Interface Flags................................................................................................................................113 Table 17.3 - Status Register .......................................................................................................................................115 Table 17.4 - Resets ....................................................................................................................................................116 Table 19.1 - Configuration Registers ..........................................................................................................................123 Table 19.2 - Chip Level Registers...............................................................................................................................125 Table 19.3 - Logical Device Registers.........................................................................................................................128 Table 19.4 - I/O Base Address Configuration Register Description..............................................................................130 Table 19.5 - Interrupt Select Configuration Register Description .................................................................................131 Table 19.6 - DMA Channel Select Configuration Register Description.........................................................................131 Table 19.7 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]...............................................133 Table 19.8 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] ..............................................................134 Table 19.9 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]..............................................................135 Table 19.10 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]............................................................136 Table 19.11 - KYBD, Logical Device 7 [Logical Device Number = 0x07] .....................................................................137 Table 19.12 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] ............................................................137 Table 19.13 - nRTS MUXING ....................................................................................................................................139 Table 19.14 - nCTS2 MUXING...................................................................................................................................139 Table 19.15 - nDTR2 MUXING ..................................................................................................................................139 Table 19.16 - nDSR2 MUXING ..................................................................................................................................140 Table 19.17 - nDCD2 MUXING ..................................................................................................................................140 Table 19.18 - nRI2 MUXING ......................................................................................................................................140 Table 19.19 - DRQ3 MUXING....................................................................................................................................140 Table 19.20 - nDACK3 MUXING................................................................................................................................141 Table 19.21 - SER_IRQ MUXING ..............................................................................................................................141 Table 19.22 - PCI_CLK MUXING...............................................................................................................................141 Table 19.23 - DRVDEN1 MUXING.............................................................................................................................141 Table 19.24 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] ............................................................141 Table 21.1 - ISA Read Timing Parameters ................................................................................................................149 Table 21.2 - EPP 1.9 Data or Address Cycle Timing Parameters ..............................................................................158 Table 21.3 - EPP 1.9 Data or Address Read Cycle Timing Parameters ....................................................................160 Table 21.4 - EPP 1.7 Data or Address Write Cycle Parameters ................................................................................162 Table 21.5 - EPP 1.7 Data or Address Read Cycle Parameters ................................................................................163 Table 23.1 - 100 Pin TQFP Package Parameters .......................................................................................................173
SMSC FDC37C672
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Enhanced Super I/O Controller with Fast IR Datasheet
Chapter 1
General Description
The FDC37C672 with Consumer IR and IrDA v1.1 support incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip 24 mA AT bus drivers, two floppy direct drive support, Intelligent power management and SMI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The FDC37C672 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37C672 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionality to support Windows '95. The I/O Address, DMA Channel and Hardware IRQ of each logical device in the FDC37C672 may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, 8 parallel IRQs, an optional Serialized IRQ interface, and three DMA channels. The FDC37C672 does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The FDC37C672 is software and register compatible with SMSC's proprietary 82077AA core.
IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation. SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation.
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Chapter 2
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
nDTR2/ SA14/IRQ7 nCTS2/ SA13/IRQ6 nRTS2 /SA12/IRQ5 nDSR2/SA15/IRQ10/nSMI TXD2/IRTX RXD2/IRRX nDCD2/P12/IRQ11 VCC nRI2/P16/IRQ12 nDCD1 nRI1 nDTR1 nCTS1 nRTS1/SYSOP nDSR1 TXD1 RXD1 nSTROBE nALF nERROR
DRVDEN0 DRVDEN1/IRMODE nMTRO nDS1 nDS0 nMTR1 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDAT A nD SKCHG VCC CLOCKI SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
FDC37C67x FDC37C672 100 PIN QFP 100 PIN QFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
nACK BUSY PE SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN n INIT VCC A20M KBDRST IRTX IRRX VSS MCLKK MDAT KCLK KDAT IOCHRDY TC VCC DRQ3/P12 nDACK3/P16
Figure 2.1 - FDC37C672 100 Pin QFP
SMSC FDC37C672
nC S/SA11 PCI_CLK/IRQ4 SER_I RQ/IRQ3 nIOR nIOW AEN SD0 SD1 SD2 SD3 VSS SD4 SD5 SD6 SD7 RESET_DRV nDACK1 DRQ2 nDACK2 DRQ1
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DRVDEN1/IRMODE DRVDEN0 nDTR2/SA14/IRQ7 nCTS2/SA13/IRQ6 nRTS2/SA12/IRQ5 nDSR2/SA15/IRQ10/nSMI TXD2/IRTX RXD2/IRRX nDCD2/P12/IRQ11 VCC nRI2/P16/IRQ12 nDCD1 nRI1 nDTR1 nCTS1 nRTS1/SYSOP nDSR1 TXD1 RXD1 nSTROBE nALF nERROR nACK BUSY PE
SMSC FDC37C672
SA8 SA9 SA10 nCS/SA11 PCI_CLK/IRQ4 SER_IRQ/IRQ3 nIOR nIOW AEN SD0 SD1 SD2 SD3 VSS SD4 SD5 SD6 SD7 RESET_DRV nDACK1 DRQ2 nDACK2 DRQ1 nDACK3/P16 DRQ3/P12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
nMTR0 nDS1 nDS0 nMTR1 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG VCC CLOCKI SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
FDC37C672 100 PIN TQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC A20M KBDRST IRTX IRRX VSS MCLK MDAT KCLK KDAT IOCHRDY TC VCC
Figure 2.2 - FDC37C672 100 Pin TQFP
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Chapter 3
PIN NO. QFP/TQFP 37:40, 42:45 / 35:38, 40:43 20:30 / 18:28 31 / 29 36 / 34 55 / 53 46 / 44 33 / 31
Description of Pin Functions
NAME TOTAL SYMBOL SD[0:7] BUFFER TYPE IO24 PROCESSOR/HOST INTERFACE (34) 8
System Data Bus
11-bit System Address Bus Chip Select/SA11 (Note 3.2) Address Enable I/O Channel Ready ISA Reset Drive Serial IRQ/Parallel IRQ_3
11 1 1 1 1 1
SA[0:10] nCS/SA11 AEN IOCHRDY RESET_DRV SER_IRQ/ IRQ3 PCI_CLK/ IRQ4 DRQ1 DRQ2 DRQ3/P12 nDACK1 nDACK2 nDACK3/ P16 TC nIOR nIOW CLOCKI IRRX IRTX VCC
I I I OD24 IS IO24/O24/ D24 (Note 3.1) IO24/O24/ OD24 (Note 3.1) O24 O24 O24/IO24 I I I/IO24 I I I ICLK I O24
32 / 30
PCI Clock for Serial IRQ (33MHz/30MHz)/ Parallel IRQ_4 DMA Request 1 DMA Request 2 DMA Request 3/8042 P12 DMA Acknowledge 1 DMA Acknowledge 2 DMA Acknowledge 3/8042 P16 Terminal Count I/O Read I/O Write CLOCKS (1) 14.318MHz Clock Input INFRARED INTERFACE (2) Infrared Rx Infrared Tx POWER PINS (8) Power
1
50 / 48 48 / 46 52 / 50 47 / 45 49 / 47 51 / 49 54 / 52 34 / 32 35 / 33 19 / 17 61 / 59 62 / 60 18,53, 65,93 / 16, 51, 63, 91 7,41, 60,76 / 5, 39, 58, 74 16 / 14 11 / 9 10 / 8
1 1 1 1 1 1 1 1 1 1 1 1
Ground FDD INTERFACE (16) Read Disk Data Write Gate Write Disk Data 1 1 1
VSS
nRDATA nWGATE nWDATA
IS O24/OD24 O24/OD24
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PIN NO. QFP/TQFP 12 /10 8/6 9/7 17 / 15 5/3 4/2 3/1 6/4 15 / 13 14 / 12 13 / 11 1 / 99 2 / 100
NAME Head Select Step Direction Step Pulse Disk Change Drive Select 0 Drive Select 1 Motor On 0 Motor On 1 Write Protected Track 0 Index Pulse Input Drive Density Select 0 Drive Density Select 1/IR Mode Select/IRRX3
TOTAL 1 1 1 1 1 1 1 1 1 1 1 1 1
SYMBOL nHDSEL nDIR nSTEP nDSKCHG nDS0 nDS1 nMTR0 nMTR1 nWRTPRT nTRKO nINDEX DRVDEN0 DRVDEN1/ IRMODE/ IRRX3 RXD1 TXD1 nRTS1/ SYSOP nCTS1 nDTR1 nDSR1 nDCD1 nRI1 RXD2/IRRX TXD2/IRTX nRTS2/SA12/IR Q5 nCTS2/SA13/IR Q6 nDTR2/SA14/I RQ7 nDSR2/SA15/I RQ10/ nSMI nDCD2/P12/ IRQ11 nRI2/P16/ IRQ12
BUFFER TYPE O24/OD24 O24/OD24 O24/OD24 IS O24/OD24 O24/OD24 O24/OD24 O24/OD24 IS IS IS O24/OD24 O24/OD24/O 24/I
84 / 82 85 / 83 87 / 85 88 / 86 89 / 87 86 / 84 91 / 89 90 / 88 95 / 93 96 / 94 98 / 96
Receive Serial Data 1 Transmit Serial Data 1 Request to Send 1 Clear to Send 1 Data Terminal Ready 1 Data Set Ready 1 Data Carrier Detect 1 Ring Indicator 1
SERIAL PORT 1 INTERFACE (8) 1 1 1 1 1 1 1 1 SERIAL PORT 2 INTERFACE (8) Receive Serial Data 2/Infrared Rx 1 Transmit Serial Data 2/Infrared Tx 1 Request to Send 2/Sys Addr 12/ Parallel IRQ_5 1
I O4 O4/I I O4 I I I I O24 O4/I/O24/ OD24 (Note 3.1) I/I/O24/ OD24 (Note 3.1) O4/I/O24/ OD24 (Note 3.1) I/I/O24/OD 24 (Note 3.1) I/IO24/O24/O D24 (Note 3.1) I/IO24/O24/O D24 (Note 3.1) IO24
99 / 97 100 / 98
Clear to Send 2/Sys Addr 13/ Parallel IRQ_6 Data Terminal Ready/Sys Addr 14/ Parallel IRQ_7
1 1
97 / 95
Data Set Ready 2/Sys Addr 15/ Parallel IRQ_10/nSMI Data Carrier Detect 2/8042 P12/ Parallel IRQ_11
1
94 / 92
1
92 / 90
Ring Indicator 2/8042 P16/Parallel IRQ_12
1
68:75 / 66:73
Parallel Port Data Bus
PARALLEL PORT INTERFACE (17) 8
PD[0:7]
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PIN NO. QFP/TQFP 67 / 65 66 / 64 82 / 80 83 / 81 79 / 77 80 / 78 78 / 76 77 / 75 81 / 79 56 / 54 57 / 55 58 / 56 59 / 57 63 / 61 64 / 62
NAME
TOTAL
SYMBOL nSLCTIN nINIT nALF nSTROBE BUSY nACK PE SLCT nERROR KDAT KCLK MDAT MCLK KBDRST (Note 3.4) A20M
Printer Select 1 Initiate Output 1 Auto Line Feed 1 Strobe Signal 1 Busy Signal 1 Acknowledge Handshake 1 Paper End 1 Printer Selected 1 Error at Printer 1 KEYBOARD/MOUSE INTERFACE (6) Keyboard Data 1 Keyboard Clock 1 Mouse Data 1 Mouse Clock 1 Keyboard Reset 1 Gate A20 1
BUFFER TYPE OD24/O24 OD24/O24 OD24/O24 OD24/O24 I I I I I IOD16P IOD16P IOD16P IOD16P O4 O4
Note 3.1 The interrupt request is output on one of the IRQx signals as an 024 buffer type. If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. In this case, the buffer type is OD24. Refer to the configuration section for more information. Note 3.2 For 12-bit addressing, SA0:SA11 only, nCS should be tied to GND. For 16-bit external address qualification, address bits SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16-bit Internal Address Qualification Mode. CR24.6 controls the FDC37C672 addressing modes. Note 3.3 The "n" as the first letter of a signal name indicates an "Active Low" signal. Note 3.4 KBDRST is active low.
3.1
Buffer Type Descriptions
I IS IOD16P IO24 IO4 O4 O24 OD24 ICLK Input, TTL compatible. Input with Schmitt trigger. Input/Output, 16mA sink, 90uA pull-up. Input/Output, 24mA sink, 12mA source. Input/Output, 4mA sink, 2mA source. Output, 4mA sink, 2mA source. Output, 24mA sink, 12mA source. Output, Open Drain, 24mA sink. Clock Input
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Chapter 4
PIN NO. QFP/TQFP 2 / 100 32 / 30 33 / 31 51 / 49 52 / 50 92 / 90 94 / 92 95 / 93 96 / 94 97 / 95 98 / 96 99 / 97 100 / 98
Description of Multifunction Pins
ALTERNATE FUNCTION 1 IR MODE IRQ4 IRQ3 8042 P16 8042 P12 8042 P16 8042 P12 IRRX IRTX SA15 SA12 SA13 SA14 ALTERNATE FUNCTION 2 IRRX3 DEFAULT DRVDEN1 PCICLK SERIRQ nDACK3 DRQ3 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 NOTE Note 4.1 Note 4.2 Note 4.2 Note 4.3 Note 4.3 Note 4.4 Note 4.4 Note 4.5 Note 4.5 Note 4.6 Note 4.6 Note 4.6 Note 4.6
ORIGINAL FUNCTION DRVDEN1 PCICLK SERIRQ nDACK3 DRQ3 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2
IRQ12 IRQ11
IRQ10 IRQ5 IRQ6 IRQ7
Note 4.1 Controlled by IRMODSEL(LD8:CRC0.0) and IRRX3SEL(LD8:CRC0.4) Note 4.2 Controlled by SERIRQSEL(LD8:CRC0.2) Note 4.3 Controlled by DMA3SEL(LD8:CRC0.1) Note 4.4 Controlled by 8042COMSEL(LD8:CRC0.3) and SERIRQSEL(LD8:CRC0.2) Note 4.5 Controlled by IR Option Register( LD5:CRF1.6) Note 4.6 Controlled by 16 bit Address Qual.(CR24.6) and SERIRQSEL(LD8:CRC0.2)
For more information, refer to Table 19.13 through Table 19.23.
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nSMI
*
SMI
WDT MULTI-MODE PARALLEL PORT/FDC MUX PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF ADDRESS BUS
DATA BUS SER_IRQ * PCI_CLK * SERIAL IRQ
nIOR nIOW AEN SA[0:12] (nCS)
*
CONFIGURATION REGISTERS
16C550 COMPATIBLE SERIAL PORT 1
TXD1, nCTS1, nRTS1 RXD1 nDSR1, nDCD1, nRI1, nDTR1
CONTROL BUS HOST CPU INTERFACE SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE RCLOCK RDATA WDATA WCLOCK DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED
* IRR3/Mode * IRRX, IRTX
SA[13-15]
*
SD[O:7] DRQ[1:3]* nDACK[1:3]
*
TXD2(IRTX), nCTS2, nRTS2 *
* RXD2(IRRX)
nDSR2, nDCD2, nRI2, nDTR2 *
TC IRQ[3:7,10:12] RESET_DRV IOCHRDY
*
8042
CLOCK GEN
KCLK KDATA MCLK MDATA GATEA20, KBDRST P12, P16 *
Vcc
Vss
ICLOCK (14.318)
nINDEX DENSEL nDS0,1 nTRK0 nDIR nMTR0,1 * nWDATA nRDATA nDSKCHG nSTEP DRVDEN0 nWRPRT nHDSEL DRVDEN1 nWGATE
* Denotes Multifunction Pins
Figure 4.1 - FDC37C672 Block Diagram
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Chapter 5
5.1
Functional Description
Super I/O Registers
The address map, shown below in Table 5.1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register.
5.2
Host Processor Interface
The host processor communicates with the FDC37C672 through a series of read/write registers. The port addresses for these registers are shown in Table 5.1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA.
Table 5.1 - Super I/O Block Addresses ADDRESS Base+(0-5) and +(7) Base+(0-7) Base1+(0-7) Base2+(0-7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 Note: BLOCK NAME Floppy Disk Serial Port Com 1 Serial Port Com 2 Parallel Port SPP EPP ECP ECP+EPP+SPP KYBD LOGICAL DEVICE 0 4 5 3 NOTES
IR Support Fast IR
7
Refer to the configuration register descriptions for setting the base address
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Chapter 6
Floppy Disk Controller
The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.
6.1
FDC Internal Registers
The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 6.1 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.
Table 6.1 - Status, Data and Control Registers PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 (Shown with base addresses of 3F0 and 370) SECONDARY R/W REGISTER ADDRESS Status Register A (SRA) R 370 Status Register B (SRB) R 371 Digital Output Register (DOR) R/W 372 Tape Drive Register (TSR) R/W 373 Main Status Register (MSR) R 374 Data Rate Select Register (DSR) W 374 Data (FIFO) R/W 375 Reserved 376 Digital Input Register (DIR) R 377 Configuration Control Register (CCR) W 377
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6.1.1
Status Register A (SRA)
Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDING 0 6 nDRV2 N/A 5 STEP 0 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0
RESET COND.
BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output.
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PS/2 Model 30 Mode 7 INT PENDING RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 0 6 DRQ 0 5 STEP F/F 0 4 3 TRK0 nHDSEL N/A 1 2 INDX N/A 1 WP N/A 0 nDIR 1
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6.1.2
Status Register B (SRB)
Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0
BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1".
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PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1
BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input.
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6.1.3
Digital Output Register (DOR)
Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 2 1 0 DMAEN nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 0
RESET COND.
BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the four drive selects DS0 -DS3, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active.
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BIT 7 MOTOR ENABLE 3 This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active. Table 6.2 - Drive Activation Values DRIVE 0 1 2 3 DOR VALUE 1CH 2DH 4EH 8FH
6.1.4
Tape Drive Register (TDR)
Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.3 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 6.3 - Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3
Table 6.4 - Internal 2 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 7 X X X 1 0 Bit 6 X X 1 X 0 Bit 5 X 1 X X 0 Bit 4 1 X X X 0 Bit1 0 0 1 1 X Bit 0 0 1 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 1 0 1 1 1 nDS0 0 1 1 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4
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Table 6.5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 7 X X X 1 0 Bit 6 X X 1 X 0 Bit 5 X 1 X X 0 Bit 4 1 X X X 0 Bit1 0 0 1 1 X Bit 0 0 1 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 1 1 1 1 nDS0 1 0 1 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5
Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0
REG 3F3
Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 Media ID1 DB6 Media ID0 DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0
REG 3F3
For this mode, MEDIA_ID[1:0] pins are gated into bits 6 and 7 of the 3F3 register. These two bits are not affected by a hard or soft reset. BIT 7 MEDIA ID 1 READ ONLY (Pin 19) (See Table 6.6) BIT 6 MEDIA ID 0 READ ONLY (Pin 20) (See Table 6.7) BITS 5 and 4 Drive Type ID - These bits reflect two of the bits of L0-CRF1. Which two bits these are depends on the last drive selected in the Digital Output Register (3F2). (See Table 6.8) BITS 3 and 2 Floppy Boot Drive - These bits reflect the value of L0-CRF1. Bit 3 = L0-CRF1-B7. Bit 2 = L0-CRF1-B6. Bits 1 and 0 - Tape Drive Select (READ/WRITE). Same as in Normal and Enhanced Floppy Mode 1. Note: L0-CRF1-B5 = Logical Device 0, Configuration Register F1, Bit 5
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Table 6.6 - Media ID1 INPUT Pin 19 0 1 MEDIA ID1 BIT 7 L0-CRF1-B5 L0-CRF1-B5 =0 =1 0 1 1 0 Table 6.7 - Media ID0 INPUT Pin 20 0 1 MEDIA ID0 BIT 6 CRF1-B4 CRF1-B4 =0 =1 0 1 1 0
Table 6.8 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 0 0 1 1 Note: Bit 0 0 1 0 1 REGISTER 3F3 - DRIVE TYPE ID Bit 5 L0-CRF2 - B1 L0-CRF2 - B3 L0-CRF2 - B5 L0-CRF2 - B7 Bit 4 L0-CRF2 - B0 L0-CRF2 - B2 L0-CRF2 - B4 L0-CRF2 - B6
L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.
6.1.5
Data Rate Select Register (DSR)
Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0
RESET COND.
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BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 6.9 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power
Table 6.9 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 Note: PRECOMPENSATION DELAY (NSEC) <2MBPS 2MBPS* 0 0.00 20.8 41.67 41.7 83.34 62.5 125.00 83.3 166.67 104.2 208.33 125 250.00 Default Default Default: See Table 6.11
*2Mbps data rate is only available if VCC = 5V.
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Table 6.10 - Data Rates DRIVE RATE DRT1 DRT0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 SEL0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 DATA RATE MFM FM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 --250 150 125 --250 250 125 --250 --125 DENSEL 1 1 0 0 1 1 0 0 1 1 0 0 DRATE(1) 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
Table 6.11 - DRVDEN Mapping DT1 0 DT0 0 DRVDEN1 (1) DRATE0 DRVDEN0 (1) DENSEL DRIVE TYPE 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2
1 0 1
0 1 1
DRATE0 DRATE0 DRATE1
DRATE1 nDENSEL DRATE0
Table 6.12 - Default Precompensation Delays DATA RATE 2 Mbps (Note 6.1) 1 Mbps 500 Kbps 300 Kbps 250 Kbps PRECOMPENSATION DELAYS 20.8 ns 41.67 ns 125 ns 125 ns 125 ns
Note 6.1 The 2Mbps data rate is only available if VCC = 5V.
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6.1.6
Main Status Register
Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer. 7 RQM 6 DIO 5 NON DMA 4 CMD BUSY 3 DRV3 BUSY 2 DRV2 BUSY 1 DRV1 BUSY 0 DRV0 BUSY
BIT 0 - 3 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte. BIT 5 NON-DMA This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
6.1.7
Data Register (FIFO)
Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger
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DMA latency without causing a disk error. Table 6.14 gives several examples of the delays with aFIFO. The data is based upon the following formula:
Threshold # x 1 DATA RATE x8 - 1.5 s = DELAY
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.
Table 6.14 - FIFO Service Delay FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes Note: MAXIMUM DELAY TO SERVICING AT 2 Mbps* DATA RATE 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s MAXIMUM DELAY TO SERVICING AT 1 Mbps DATA RATE 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s MAXIMUM DELAY TO SERVICING AT 500 Kbps DATA RATE 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s
*The 2 Mbps data rate is only available if VCC = 5V.
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6.1.8
Digital Input Register (DIR)
Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG N/A 6 5 4 3 2 1 0
RESET COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]). PS/2 Mode 7 DSK CHG N/A 6 1 N/A 5 1 N/A 4 1 N/A 3 1 N/A 2 1 0 DRATE DRATE nHIGH SEL1 SEL0 nDENS N/A N/A 1
RESET COND.
BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BITS 3 - 6 UNDEFINED Always read as a logic "1" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
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Model 30 Mode 7 DSK CHG N/A 6 0 0 5 0 0 4 0 0 3 2 1 0 DMAEN NOPREC DRATE DRATE SEL1 SEL0 0 0 1 0
RESET COND.
BITS 0 - 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
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6.1.9
Configuration Control Register (CCR)
Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 5 4 3 2 1 0 DRATE DRATE SEL1 SEL0 1 0
RESET COND.
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 6.10 for the appropriate values. BIT 2 - 7 RESERVED Should be set to a logical "0"
PS/2 Model 30 Mode 7 6 5 4 3 2 1 0 NOPREC DRATE DRATE SEL1 SEL0 N/A 1 0
RESET COND.
N/A
N/A
N/A
N/A
N/A
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 6.10 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 6.11 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.
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6.1.10 Status Register Encoding
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed.
Table 6.15 - Status Register 0 BIT NO. 7,6 SYMBOL IC NAME Interrupt Code DESCRIPTION 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). The TRK0 pin failed to become a "1" after: 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". The current head address. The current selected drive.
5 4
SE EC
Seek End Equipment Check
3 2 1,0
H DS1,0
Head Address Drive Select
Table 6.16 - Status Register 1 BIT NO. 7 SYMBOL EN NAME End of Cylinder DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command.
6 5 4
DE OR
Data Error Overrun/ Underrun
3 2
ND
No Data
1
NW
Not Writable
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BIT NO. 0
SYMBOL MA
NAME Missing Address Mark
DESCRIPTION Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.
Table 6.17 - Status Register 2 BIT NO. 7 6 SYMBOL CM NAME Control Mark DESCRIPTION Unused. This bit is always "0". Any one of the following: Read Data command - the FDC encountered a deleted data address mark. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. The FDC cannot detect a data address mark or a deleted data address mark.
5 4 3 2 1
DD WC
Data Error in Data Field Wrong Cylinder
BC
Bad Cylinder
0
MD
Missing Data Address Mark
Table 6.18 - Status Register 3 BIT NO. 7 6 5 4 3 2 1,0 SYMBOL WP T0 HD DS1,0 NAME Write Protected Track 0 Head Address Drive Select DESCRIPTION Unused. This bit is always "0". Indicates the status of the WP pin. Unused. This bit is always "1". Indicates the status of the TRK0 pin. Unused. This bit is always "1". Indicates the status of the HDSEL pin. Indicates the status of the DS1, DS0 pins.
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6.2
RESET
There are three sources of system reset on the FDC: the RESET pin of the FDC, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.
6.2.1
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.
6.2.2
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.
6.3
Modes of Operation
The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the IDENT and MFM bits 6 and 5 respectively of CRxx.
6.3.1
PC/AT mode - (IDENT high, MFM a "don't care")
The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (FINTR and DRQ can be hi Z), and TC and DENSEL become active high signals.
6.3.2
PS/2 mode - (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low.
6.3.3
Model 30 mode - (IDENT low, MFM low)
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (FINTR and DRQ can be hi Z), TC is active high and DENSEL is active low.
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6.4
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. The FDC37C672 supports two DMA transfer modes for the FDC: Single Transfer and Burst Transfer. In the case of the single transfer, the DMA Req goes active at the start of the DMA cycle, and the DMA Req is deasserted after the nDACK. In the case of the burst transfer, the Req is held active until the last transfer (independent of nDACK). See timing diagrams for more information. Burst mode is enabled via Bit[1] of CRF0 in Logical Device 0. Setting Bit[1]=0 enables burst mode; the default is Bit[1]=1, for non-burst mode.
6.5
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections.
6.5.1
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 7.1 for the command set descriptions.) These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition.
6.5.2
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or nonDMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
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A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode - Transfers from the FIFO to the Host The FINT pin and RQM bits in the Main Status Register are activated when the FIFO contains (16) bytes or the last bytes of a full sector have been placed in the FIFO. The FINT pin can be used for interrupt-driven systems, and RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the FINT pin and RQM bit when the FIFO becomes empty. Non-DMA Mode - Transfers from the Host to the FIFO The FINT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the FIFO. The FINT pin and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has bytes remaining in the FIFO. The FINT pin will also be deactivated if TC and nDACK both go inactive. The FDC enters the result phase after the last byte is taken by the FDC from the FIFO (i.e. FIFO empty condition). DMA Mode - Transfers from the FIFO to the Host The FDC activates the DDRQ pin when the FIFO contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DDRQ pin when the FIFO becomes empty. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nDACK). A data underrun may occur if FDRQ is not removed in time to prevent an unwanted cycle. DMA Mode - Transfers from the Host to the FIFO. The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA controller must respond by activating the nDACK and nIOW pins and placing data in the FIFO. FDRQ remains active until the FIFO becomes full. FDRQ is again set true when the FIFO has bytes remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOW of the last byte, if no edge is present on nDACK). A data overrun may occur if FDRQ is not removed in time to prevent an unwanted cycle.
6.5.3
Data Transfer Termination
The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a hardware TC was received. The only difference between these implicit functions and TC is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the
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transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.
6.5.4
Result Phase
The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command.
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Chapter 7
Command Set/Descriptions
Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 7.1 for explanations of the various symbols used. Chapter 8 lists the required parameters and the results associated with each command that the FDC is capable of performing. Table 7.1 - Description of Command Symbols SYMBOL C D D0, D1, D2, D3 DIR DS0, DS1 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. Direction Control If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. DRIVE DS0 Disk Drive Select DS1 drive 0 0 0 drive 1 1 0 drive 2 0 1 drive 3 1 1 Special Sector Size By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. Enable Count When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). Enable Implied Seek When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. End of Track The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. Head Load Time The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. Head Unload Time The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) NAME Cylinder Address Data Pattern Drive Select 0-3
DTL
EC EFIFO EIS
EOT GAP GPL H/HDS HLT HUT
LOCK
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SYMBOL MFM MT
NAME MFM/FM Mode Selector Multi-Track Selector
N
Sector Size Code
NCN ND
New Cylinder Number Non-DMA Mode Flag
DESCRIPTION A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. SECTOR SIZE N 128 bytes 00 256 bytes 01 512 bytes 02 1024 bytes 03 ... .. The desired cylinder number. When set to 1, indicates that the FDC is to operate in the non-DMA mode. In this mode, the host is interrupted for each data transfer. When set to 0, the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH. The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. The number of sectors per track to be initialized by the Format command. The number of sectors per track to be verified during a Verify command when EC is set. When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays.
OW PCN POLL PRETRK R
Overwrite Present Cylinder Number Polling Disable Precompensation Start Track Number Sector Address
RCN SC
Relative Cylinder Number Number of Sectors Per Track Skip Flag
SK
SRT
Step Rate Interval
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SYMBOL ST0 ST1 ST2 ST3 WGATE
NAME Status 0 Status 1 Status 2 Status 3 Write Gate
DESCRIPTION Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing of WE to allow for pre-erase loads in perpendicular drives.
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Chapter 8
PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R
Instruction Set
D7 MT 0 READ DATA DATA BUS D6 D5 D4 D3 D2 D1 D0 REMARKS MFM SK 0 0 1 1 0 Command Codes 0 0 0 0 HDS DS1 DS0 Sector ID information prior to C Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Com ST0 mand execution. ST1 ST2 Sector ID information after Com C mand execution. H R N
PHASE Command
R/W W W W W W W W W W
D7 MT 0
Execution Result R R R R R R R
READ DELETED DATA DATA BUS D6 D5 D4 D3 D2 D1 D0 REMARKS MFM SK 0 1 1 0 0 Command Codes 0 0 0 0 HDS DS1 DS0 Sector ID information prior to C Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Com ST0 mand execution. ST1 ST2 Sector ID information after Com C mand execution. H R N
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PHASE Command
R/W W W W W W W W W W
D7 MT 0
Execution Result R R R R R R R
WRITE DATA DATA BUS D6 D5 D4 D3 D2 D1 D0 REMARKS MFM 0 0 0 1 0 1 Command Codes 0 0 0 0 HDS DS1 DS0 Sector ID information prior to C Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Com ST0 mand execution. ST1 ST2 Sector ID information after C Command execution. H R N
PHASE Command
R/W W W W W W W W W W
D7 MT 0
WRITE DELETED DATA DATA BUS D6 D5 D4 D3 D2 D1 MFM 0 0 1 0 0 0 0 0 0 HDS DS1 C H R N EOT GPL DTL
D0 1 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
Execution Result R R R R R R R ST0 ST1 ST2 C H R N
Data transfer between the FDD and system. Status information after Command execution.
Sector ID information after Command execution.
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PHASE Command
R/W W W W W W W W W W
D7 0 0
READ A TRACK DATA BUS D6 D5 D4 D3 D2 D1 MFM 0 0 0 0 1 0 0 0 0 HDS DS1 C H R N EOT GPL DTL
D0 0 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
Execution
Result
R R R R R R R
ST0 ST1 ST2 C H R N
Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Status information after Command execution.
Sector ID information after Command execution.
PHASE Command
R/W W W W W W W W W W
D7 MT EC
VERIFY DATA BUS D6 D5 D4 D3 D2 D1 MFM SK 1 0 1 1 0 0 0 0 HDS DS1 C H R N EOT GPL DTL/SC
D0 0 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
Execution Result R R R R R R R ST0 ST1 ST2 C H R N
No data transfer takes place. Status information after Command execution.
Sector ID information after Command execution.
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PHASE Command Result
R/W W R
D7 0 1
D6 0 0
D5 0 0
VERSION DATA BUS D4 D3 D2 1 0 0 1 0 0
D1 0 0
D0 0 0
REMARKS Command Code Enhanced Controller
PHASE Command
R/W W W W W W W W W W W
D7 0 0
FORMAT A TRACK DATA BUS D6 D5 D4 D3 D2 D1 MFM 0 0 1 1 0 0 0 0 0 HDS DS1 N SC GPL D C H R N
D0 1 DS0
REMARKS Command Codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters
Execution for Each Sector Repeat:
Result
R R R R R R R
ST0 ST1 ST2 Undefined Undefined Undefined Undefined
FDC formats an entire cylinder Status information after Command execution
PHASE Command Execution
R/W W W
D7 0 0
D6 0 0
D5 0 0
RECALIBRATE DATA BUS D4 D3 D2 D1 0 0 1 1 0 0 0 DS1
D0 1 DS0
REMARKS Command Codes Head retracted to Track 0 Interrupt.
PHASE Command Result
R/W W R R
D7 0
SENSE INTERRUPT STATUS DATA BUS D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 ST0 PCN
REMARKS Command Codes Status information at the end of each seek operation.
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PHASE Command
R/W W W W
SPECIFY DATA BUS D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 SRT HUT HLT ND
REMARKS Command Codes
PHASE Command Result
R/W W W R
D7 0 0
D6 0 0
SENSE DRIVE STATUS DATA BUS D5 D4 D3 D2 D1 0 0 0 1 0 0 0 0 HDS DS1 ST3
D0 0 DS0
REMARKS Command Codes Status information about FDD
PHASE Command
R/W W W W
D7 0 0
D6 0 0
SEEK DATA BUS D5 D4 D3 D2 D1 0 0 1 1 1 0 0 0 HDS DS1 NCN
D0 1 DS0
REMARKS Command Codes
Execution
Head positioned over proper cylinder on diskette.
PHASE Command
Execution
R/W W W W W
D7 0 0 0
D6 0 0 EIS
CONFIGURE DATA BUS D5 D4 D3 D2 D1 D0 0 1 0 0 1 1 0 0 0 0 0 0 EFIFO POLL FIFOTHR PRETRK
REMARKS Configure Information
PHASE Command
R/W W W W
D7 1 0
D6 DIR 0
RELATIVE SEEK DATA BUS D5 D4 D3 D2 D1 0 0 1 1 1 0 0 0 HDS DS1 RCN
D0 1 DS0
REMARKS
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PHASE Command
R/W W
D7 0
D6 0
D5 0
DUMPREG DATA BUS D4 D3 0 1
D2 1
D1 1
D0 0
REMARKS *Note: Registers placed in FIFO
Execution Result
R R R R R R R R R R
PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 SRT HUT HLT ND SC/EOT LOCK 0 D3 D2 D1 D0 GAP WGATE 0 EIS EFIFO POLL FIFOTHR PRETRK
PHASE Command Execution
R/W W W
D7 0 0
D6 MFM 0
D5 0 0
READ ID DATA BUS D4 D3 D2 0 1 0 0 0 HDS
D1 1 DS1
D0 0 DS0
REMARKS Commands The first correct ID information on the Cylinder is stored in Data Register Status information after Command execution. Disk status after the Command has completed
Result
R
ST0
R R R R R R
ST1 ST2 C H R N
PHASE Command
R/W W
D7 0 OW
D6 0 0
PERPENDICULAR MODE DATA BUS D5 D4 D3 D2 D1 0 1 0 0 1 D3 D2 D1 D0 GAP
D0 0 WGATE
REMARKS Command Codes
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PHASE Command Result
R/W W R
D7
INVALID CODES DATA BUS D6 D5 D4 D3 D2 D1 Invalid Codes ST0
D0
REMARKS Invalid Command Codes (NoOp FDC goes into Standby State) ST0 = 80H
PHASE Command Result
R/W W R
D7 LOCK 0
D6 0 0
D5 0 0
LOCK DATA BUS D4 D3 1 0 LOCK 0
D2 1 0
D1 0 0
D0 0 0
REMARKS Command Codes
SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
8.1
Data Transfer Commands
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed.
8.1.1
Read Data
A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of TC, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 8.1 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred.
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Table 8.1 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes
The amount of data which can be handled with a single command to the FDC depends upon MT (multitrack) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 8.2. At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 8.3 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 8.3, the C or R value of the sector address is automatically incremented (see Table 8.5).
Table 8.2 - Effects of MT and N Bits MT 0 1 0 1 0 1 N 1 1 2 2 3 3 MAXIMUM TRANSFER CAPACITY 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 FINAL SECTOR READ FROM DISK 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
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Table 8.3 - Skip Bit vs Read Data Command SK BIT VALUE DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ? 0 0 1 1 Normal Data Deleted Data Normal Data Deleted Data Yes Yes Yes No RESULTS CM BIT OF ST2 SET? No Yes No Yes DESCRIPTION OF RESULTS Normal termination. Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped").
8.1.2
Read Deleted Data
This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 8.4 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 8.4, the C or R value of the sector address is automatically incremented (see Table 8.5). Table 8.4 - Skip Bit vs. Read Deleted Data Command
SK BIT VALUE
DATA ADDRESS MARK TYPE ENCOUNTERED SECTOR READ?
RESULTS CM BIT OF ST2 SET? Yes DESCRIPTION OF RESULTS Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). Normal termination.
0
Normal Data
Yes
0 1
Deleted Data Normal Data
Yes No
No Yes
1
Deleted Data
Yes
No
8.1.3
Read A Track
This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID
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information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a "1" if there is no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.
Table 8.5 - Result Phase Table MT 0 HEAD 0 1 1 0 1 Notes: NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented. FINAL SECTOR TRANSFERRED TO HOST Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT ID INFORMATION AT RESULT PHASE C NC C+1 NC C+1 NC NC NC C+1 H NC NC NC NC NC LSB NC LSB R R+1 01 R+1 01 R+1 01 R+1 01 N NC NC NC NC NC NC NC NC
8.1.4
Write Data
After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command Definition of DTL when N = 0 and when N does not = 0
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8.1.5
Write Deleted Data
This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk.
8.1.6
Verify
The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, TC (pin 89) cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 8.5 and Table 8.6 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". Table 8.6 - Verify Command Result Phase Table
MT 0 0 0 0 1 1 1 1 Note:
EC 0 0 1 1 0 0 1 1
SC/EOT VALUE SC = DTL EOT # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC # Sectors Remaining AND EOT # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC # Sectors Remaining AND EOT # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side
TERMINATION RESULT Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid
If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk.
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8.1.7
Format A Track
The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the IDX pin again and it terminates the command. Table 8.7 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. Table 8.7 - Format Fields SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM 3x FC C2 GAP1 SYNC 50x 12x 4E 00 IDAM 3x FE A1 C Y L H D S N C GAP2 SYNC EOR 22x 12x C C 4E 00 DATA AM 3x FB A1 F8 C DATA R GAP3 GAP 4b C
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a 40x FF SYNC 6x 00 IAM FC GAP1 SYNC 26x 6x FF 00 IDAM FE C Y L H D S N C GAP2 SYNC EOR 11x 6x C C FF 00 DATA AM FB or F8 C DATA R GAP3 GAP 4b C
PERPENDICULAR FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM 3x FC C2 GAP1 SYNC 50x 12x 4E 00 IDAM 3x FE A1 C Y L H D S N C GAP2 SYNC EOR 41x 12x C C 4E 00 DATA AM 3x FB A1 F8 C DATA R GAP3 GAP 4b C
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Table 8.8 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 1024 2048 4096 ... 256 256 512* 1024 2048 4096 ... 128 256 512 256 512** 1024 N 00 00 02 03 04 05 ... 01 01 02 03 04 05 ... 0 1 2 1 2 3 SC 12 10 08 04 02 01 12 10 09 04 02 01 0F 09 05 0F 09 05 GPL1 07 10 18 46 C8 C8 0A 20 2A 80 C8 C8 07 0F 1B 0E 1B 35 GPL2 09 19 30 87 FF FF 0C 32 50 F0 FF FF 1B 2A 3A 36 54 74
FM 5.25" Drives
MFM
3.5" Drives
FM
MFM
GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex.
8.2
Control Commands
Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt.
8.2.1
Read ID
The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost.
8.2.2
Recalibrate
This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTR0 pin from the FDD. As long as the nTR0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTR0 pin goes high, the
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SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTR0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller.
8.2.3
Seek
The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: PCN > NCN: Direction signal to drive set to Direction signal to drive set to "1" (step in) and issues step pulses. "0" (step out) and issues step pulses.
The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. Note that if implied seek is not enabled, the read and write commands should be preceded by: 1. 2. 3. 4. Seek command - Step to the proper track Sense Interrupt Status command - Terminate the Seek command Read ID - Verify head is on proper track Issue Read/Write command.
The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command be issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command.
8.2.4
Sense Interrupt Status
An interrupt signal on FINT pin is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command
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2. 3.
f. Format A Track command g. Write Deleted Data command h. Verify command End of Seek, Relative Seek, or Recalibrate command FDC requires a data transfer during the execution phase in the non-DMA mode
The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. Table 8.9 - Interrupt Identification SE 0 1 IC 11 00 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command
1
01
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command.
8.2.5
Sense Drive Status
Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information.
8.2.6
Specify
The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 8.10. The values are the same for MFM and FM.
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Table 8.10 - Drive Control Delays (ms) 2M 64 4 .. 56 60 1M 128 8 .. 112 120 HUT 500K 300K 426 256 26.7 16 .. .. 373 224 400 240 250K 512 32 .. 448 480 2M 4 3.75 .. 0.5 0.25 HLT 00 01 02 .. 7F 7F 2M 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 300K 426 3.3 6.7 .. 420 423 250K 512 4 8 . 504 508 1M 8 7.5 .. 1 0.5 SRT 500K 300K 26.7 16 25 15 .. .. 3.33 2 1.67 1 250K 32 30 .. 4 2
0 1 .. E F
The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by the FDRQ pin. Non-DMA mode uses the RQM bit and the FINT pin to signal data transfers.
8.2.7
Configure
The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes.
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PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255.
8.2.8
Version
The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte.
8.2.9
Relative Seek
The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control DIR 0 1 ACTION Step Head Out Step Head In
RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command.
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8.2.10 Perpendicular Mode
The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 8.11 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown in Table 8.7 - Format Fields illustrates the change in the Gap2 field size for the perpendicular format. On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC as shown on page 57. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. 2. 3. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. The write pre-compensation given to a perpendicular mode drive will be 0ns. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation.
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Note:
Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0-D3 are ignored. Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. 2. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. "Hardware" resets will clear all bits
(GAP, WGATE and D0-D3) to "0", i.e. all conventional mode. Table 8.11 - Effects of WGATE and GAP Bits PORTION OF GAP 2 WRITTEN BY WRITE DATA OPERATION 0 Bytes 19 Bytes 0 Bytes 38 Bytes
WGATE 0 0 1 1
GAP MODE Conventional 0 Perpendicular 1 (500 Kbps) Reserved 0 (Conventional) Perpendicular 1 (1 Mbps)
LENGTH OF GAP2 FORMAT FIELD 22 Bytes 22 Bytes 22 Bytes 41 Bytes
8.3
LOCK
In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte.
8.4
Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands.
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8.5
Compatibility
The FDC37C672 was designed with software compatibility in mind. It is a fully backwards-compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.
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Chapter 9
Serial Port (UART)
The FDC37C672 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA, HP-SIR, ASK-IR, Fast IR and Consumer IR infrared modes of operation. Note: The UARTs may be configured to share an interrupt. information. Refer to the Configuration section for more
9.1
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37C672 contains two serial ports, each of which contain a register set as described below. Table 9.1 - Addressing the Serial Port DLAB (Note 9.1) 0 0 0 X X X X X X X 1 1 A2 0 0 0 0 0 0 1 1 1 1 0 0 A1 0 0 0 1 1 1 0 0 1 1 0 0 A0 0 0 1 0 0 1 0 1 0 1 0 1 REGISTER NAME Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write) Scratchpad (read/write) Divisor LSB (read/write) Divisor MSB (read/write
Note 9.1 DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers.
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9.1.1
Receive Buffer Register (RB)
Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.
9.1.2
Transmit Buffer Register (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete.
9.1.3
Interrupt Enable Register (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37C672. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These bits are always logic "0".
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9.1.4
FIFO Control Register (FCR)
Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level.
Note:
DMA is not supported. The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (LD8:CRC3[7:0]) and UART2 FIFO Control Shadow Register (LD8:CRC4[7:0]). Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Bit 4,5 Reserved Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt.
9.1.5
Interrupt Identification Register (IIR)
Address Offset = 2H, DLAB = X, READ BIT 7 0 0 1 1 BIT 6 0 1 0 1 RCVR FIFO TRIGGER LEVEL (BYTES) 1 4 8 14
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority:
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1. 2. 3. 4.
Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic "0". Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
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Table 9.2 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 0 1 BIT 1 0 1 BIT 0 1 0 PRIORITY LEVEL Highest INTERRUPT SET AND RESET FUNCTIONS INTERRUPT SOURCE None None Receiver Line Status Overrun Error, Parity Error, Framing Error or Break Interrupt Received Data Receiver Data Available Available INTERRUPT TYPE INTERRUPT RESET CONTROL Reading the Line Status Register Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register
0
1
0
0
Second
1
1
0
0
Second
Character Timeout Indication
0
0
1
0
Third
Transmitter Holding Register Empty
0
0
0
0
Fourth
MODEM Status
No Characters Have Been Removed From or Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Transmitter Holding Reading the IIR Register Empty Register (if Source of Interrupt) or Writing the Transmitter Holding Register Clear to Send or Reading the Data Set Ready or MODEM Status Ring Indicator or Register Data Carrier Detect
9.1.6
Line Control Register (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: BIT 1 0 0 1 1 BIT 0 0 1 0 1 WORD LENGTH 5 Bits 6 Bits 7 Bits 8 Bits
The Start, Stop and Parity bits are not included in the word length.
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Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. BIT 2 0 1 1 1 1 Note: WORD LENGTH -5 bits 6 bits 7 bits 8 bits NUMBER OF STOP BITS 1 1.5 2 2 2
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. Bit 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. Bit 5 Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4. Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
9.1.7
Modem Control Register (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1".
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Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1. 2. 3. 4. 5. 6. 7. The TXD is set to the Marking State(logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7 These bits are permanently set to logic zero.
9.1.8
Line Status Register (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE
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indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty, Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO.
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9.1.9
Modem Status Register (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.
Note:
Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated. Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR.
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9.1.10 Scratchpad Register (SCR)
Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. scratchpad register to be used by the programmer to hold data temporarily. It is intended as a
9.2
Programmable Baud Rate Generator (and Divisor Latches DLH, DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of taking any clock input (DC to 3 MHz) and dividing it by any divisor from 1 to 65535. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 9.3 shows the baud rates possible with a 1.8462 MHz crystal.
9.2.1
Effect Of The Reset on Register File
The Reset Function Table (Table 9.4) details the effect of the Reset input on each of the registers of the Serial Port.
9.3
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0)is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: A. A FIFO timeout interrupt occurs if all the following conditions exist: At least one character is in the FIFO. The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay). The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate).
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C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. B. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
9.4
FIFO Polled Mode Operation
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters.
Table 9.3 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 DIVISOR USED TO GENERATE 16X CLOCK 2304 1536 1047 857 768 384 192 96 64 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL (Note 9.2) 0.001 0.004 CRXX: BIT 7 OR 6 X X X X X X X X X
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DESIRED BAUD RATE 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800
DIVISOR USED TO GENERATE 16X CLOCK 58 48 32 24 16 12 6 3 2 1 32770 32769
PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL (Note 9.2) 0.005 0.030 0.16 0.16 0.16 0.16
CRXX: BIT 7 OR 6 X X X X X X X X X X 1 1
Note 9.2 The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Table 9.4 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0 RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5, 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High High All Bits Low All Bits Low
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Table 9.5 - Register Summary for an Individual UART Channel REGISTER SYMBOL BIT 0
Data Bit 0 (Note 9.4) Data Bit 0 Enable Received Data Available Interrupt (ERDAI) Enable Transmitter Holding Register Empty Interrupt (ETHREI) Enable Receiver Line Status Interrupt (ELSI) Enable MODEM Status Interrupt (EMSI) 0 0 Interrupt ID Bit RCVR FIFO Reset Word Length Select Bit 1 (WLS1) Number of Stop Bits (STB) XMIT FIFO Reset Interrupt ID Bit Interrupt ID Bit (Note 9.8) 0 0 "0" if Interrupt Pending FIFO Enable Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 6 0
REGISTER ADDRESS BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
RBR THR IER
REGISTER NAME
BIT 7
Data Bit 7 Data Bit 7 0
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write Only)
(Note 9.3) ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0
Interrupt Enable Register
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
FIFOs Enabled (Note 9.8) Reserved Reserved
FIFOs Enabled (Note 9.8) RCVR Trigger RCVR LSB Trigger MSB Even Parity Select (EPS) Loop Break Interrupt (BI) Clear to Send (CTS) Stick Parity Set Break
ADDR = 2
FIFO Control Register (Write Only)
FCR (Note 9.10) LCR Word Length Select Bit 0 (WLS0) Data Terminal Request to Ready (DTR) Send (RTS) Data Ready (DR) Overrun Error (OE)
ADDR = 3
Line Control Register
DMA Mode Select (Note 9.9) Parity Enable (PEN)
ADDR = 4 LSR
MODEM Control Register
MCR
0 Transmitter Holding Register (THRE) Data Set Ready (DSR)
0
Divisor Latch Access Bit (DLAB) 0 OUT2 (Note 9.6) Framing Error (FE)
ADDR = 5
Line Status Register
OUT1 (Note 9.6) Parity Error (PE)
ADDR = 6
MODEM Status Register
MSR
Delta Clear to Send (DCTS)
Delta Data Set Ready (DDSR) Bit 1 Bit 1
Transmitter Empty (TEMT) (Note 9.5) Ring Indicator (RI)
Scratch Register (Note 9.8) Divisor Latch (LS) DLM Bit 8
SCR DDL
Bit 0 Bit 0
Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 9 Bit 10
Delta Data Carrier Detect (DDCD) Bit 3 Bit 3 Bit 11
Bit 4 Bit 4 Bit 12
Bit 5 Bit 5 Bit 13
Bit 6 Bit 6 Bit 14
Error in RCVR FIFO (Note 9.8) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1
Divisor Latch (MS)
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Note 9.3 DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 9.4 Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 9.5 When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. Note 9.6 This bit no longer has a pin associated with it. Note 9.7 When operating in the XT mode, this register is not available. Note 9.8 These bits are always zero in the non-FIFO mode. Note 9.9 Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 9.10 The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
9.5
9.5.1
Notes on Serial Port Operation
FIFO Mode Operation:
GENERAL The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs.
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One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).
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Chapter 10 Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional IRTX and IRRX pins. These can be selected through the configuration registers. IrDA allows serial communication at baud rates up to 4 Mbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed IR allows serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform. If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments.
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Chapter 11 Fast IR
The following is a description of the top level connection for the Fast IR block in the FDC37C672. Refer to the Infrared Communications Controller Specification for more information on Fast IR. There are two types of transceiver modules used for Fast IR: one has a mode pin (IR Mode) to control it, and the other has a second receive data channel (IRRX3). The FDC37C672 has two configuration bits that can be used for these signals. These are IRMODESEL and IRRX3SEL. The following table illustrates the selection of the functions.
Table 11.1 - DRVDEN1 MUXING MUX CONTROLS PIN NAME DRVDEN1 IRMODESEL (LD8:CRC0.0) 0 1 1 IRRX3SEL (LD8:CRC0.4) X 0 1 SELECTED FUNCTION DRVDEN1 (default) IRMODE (Note 11.1) IRRX3 STATE OF UNCONNECTED INPUTS 0
Note 11.1 IRRX3SEL Default (0). The figure below is the IR interface block diagram.
RA CO TV AS IR IrD FIR aux CO G.P. FAST
IRRX3SE L FAS T DRV_DEN 1 IRMOD E RX2 1 0 RX1 1 0
TX1
TXD RXD
TX2
IRT IRR DRVDE
1 0
FD
IRMODESE L
Figure 11.1 - IR Interface Block Diagram
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Chapter 12 Parallel Port
The FDC37C672 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The FDC37C672 also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below: DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT BASE ADDRESS + 00H BASE ADDRESS + 01H BASE ADDRESS + 02H BASE ADDRESS + 03H EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 BASE ADDRESS + 04H BASE ADDRESS + 05H BASE ADDRESS + 06H BASE ADDRESS + 07H
The bit map of these registers is: DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 D0 PD0 TMOUT STROBE PD0 PD0 PD0 PD0 PD0 D1 PD1 0 AUTOFD PD1 PD1 PD1 PD1 PD1 D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2 D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3 D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 AD7 PD7 PD7 PD7 PD7 NOTE
Note 12.1 Note 12.1 Note 12.1 Note 12.2 Note 12.3 Note 12.2 Note 12.3 Note 12.2 Note 12.3 Note 12.2 Note 12.3 Note 12.2 Note 12.3
Note 12.1 These registers are available in all modes. Note 12.2 These registers are only available in EPP mode. Note 12.3 For EPP mode, IOCHRDY must be connected to the ISA bus.
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Table 12.1 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode Note: PIN NUMBER STANDARD nStrobe PData<0:7> nAck Busy PE Select nAutofd nError nInit nSelectin EPP nWrite PData<0:7> Intr nWait (NU) (NU) nDatastb (NU) (NU) nAddrstrb ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) nInit(1) nReverseRqst(3) nSelectIn(1,3)
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.
12.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes
DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU. STATUS PORT ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of an nIOR read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
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BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected. BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character. CONTROL PORT ADDRESS OFFSET = 02H The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled.
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BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. EPP ADDRESS PORT ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
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EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated. EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of operation 1. 2. 3. 4. 5. 6. 7. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. a. The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b. The chip latches the data from the SData bus for the PData bus and asserts (releases) IOCHRDY allowing the host to complete the write cycle. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
8. 9.
EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances:
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1. 2.
If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.
Read Sequence of Operation 1. 2. 3. 4. 5. The host selects an EPP register and drives nIOR active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 6. Peripheral drives PData bus valid. 7. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 8. a. The chip latches the data from the PData bus for the SData bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. b. The chip drives the valid data onto the SData bus and asserts (releases) IOCHRDY allowing the host to complete the read cycle. 9. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tristated. 10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1. 2. 3. 4. 5. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip places address or data on PData bus. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs.
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6. 7.
When the host deasserts nIOW the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. 2. 3. 4. 5. 6. 7. 8. 9. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. The host selects an EPP register and drives nIOR active. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. The Peripheral drives PData bus valid. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. When the host deasserts nIOR the chip deasserts nDATASTB or nADDRSTRB. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 12.2 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE O I/O I I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP.) This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. It is used to denote data read or write operation. This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. It is used to denote address read or write operation. Same as SPP mode. Same as SPP mode. Same as SPP mode. This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress.
DATASTB RESET ADDRSTB PE SLCT nERR PDIR
nData Strobe nReset nAddress Strobe Paper End Printer Selected Status Error Parallel Port Direction
O O O I I I O
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Notes: SPP and EPP can use 1 common register. nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low.
12.2
Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers Permits the use of adaptive signal timing Peer-to-peer capability
12.2.1 Vocabulary
The following terms are used in this document: assert: forward: reverse: Pword: 1 0 When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. Host to Peripheral communication. Peripheral to Host communication A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8 bits. A high level. A low level.
These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft.
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The bit map of the Extended Parallel Port registers is: data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr 0 compress 0 intrValue MODE 0 D7 PD7 Addr/RLE nBusy 0 D6 PD6 D5 PD5 D4 D3 D2 PD4 PD3 PD2 Address or RLE field Select ackIntEn nFault SelectIn 0 nInit D1 PD1 D0 PD0 NOTE Note 12.5 Note 12.4 Note 12.4 Note 12.5 Note 12.5 Note 12.5
nAck 0
PError Direction
0 autofd
0 strobe
Parallel Port Data FIFO ECP Data FIFO Test FIFO 1 0 Parallel Port IRQ nErrIntrEn dmaEn 0 0 Parallel Port DMA serviceIntr full empty 0
Note 12.4 These registers are available in all modes. Note 12.5 All FIFOs use one common 16 byte FIFO. Note 12.6 The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers.
12.3
ISA Implementation Standard
This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional.
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Table 12.3 - ECP Pin Descriptions NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode.
PError (nAckReverse) Select nAutoFd (HostAck)
I
I O
nFault (nPeriphRequest)
I
nInit
O
nSelectIn
O
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12.3.1 Register Definitions
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined. Table 12.4 - ECP Register Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS (Note 12.7) +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note 12.7 These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 12.8 All addresses are qualified with AEN. Refer to the AEN pin definition.
Table 12.5 - Mode Descriptions MODE 000 001 010 011 100 101 110 111 DESCRIPTION (Note 12.9) SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) (Reserved) Test mode Configuration mode
Note 12.9 Refer to ECR Register Description
DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output
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onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet . DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H The Control Register is located at an offset of '02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed.
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BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines.
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The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! BIT 6 intrValue Returns the value on the ISA iRq line to determine possible conflicts. BITS [3:0] Parallel Port IRQ Refer to Table 12.6B. BITS [2:0] Parallel Port DMA Refer to Table 12.6C. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all
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This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: 0: Disables the interrupt generated on the asserting edge of nFault. Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr.
BIT 3 dmaEn Read/Write 1: 0: Enables DMA (DMA starts when serviceIntr is 0). Disables DMA unconditionally.
BIT 2 serviceIntr Read/Write 1: 0: Disables DMA and all of the service interrupts. Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt.
case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: 0: The FIFO cannot accept another byte or the FIFO is completely full. The FIFO has at least 1 free byte.
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BIT 0 empty Read only 1: 0: The FIFO is completely empty. The FIFO contains at least 1 byte of data.
Table 12.6A - Extended Control Register R/W 000: MODE Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register L3-CRF0. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull).
001:
010:
011:
100: 101: 110: 111:
Table 12.6B CONFIG REG B IRQ SELECTED BITS 5:3 15 110 14 101 11 100 10 011 9 010 7 001 5 111 All Others 000
Table 12.6C CONFIG REG B DMA SELECTED BITS 2:0 3 011 2 010 1 001 All Others 000
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12.4
Operation
12.4.1 Mode Switching/Software Control
Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: Set Set Set Set Direction = 0, enabling the drivers. strobe = 0, causing the nStrobe signal to default to the deasserted state. autoFd = 0, causing the nAutoFd signal to default to the deasserted state. mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware.
Table 12.7 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 0 1 D[6:0] Run-Length Count (0-127) (mode 0011 0X00 only) Channel Address (0-127)
12.4.2 Data Compression
The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided.
12.4.3 Pin Definition
The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes.
12.4.4 ISA Connections
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section.) Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals.
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12.4.5 Interrupts
The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 serviceIntr = 0 Disables the DMA and all of the service interrupts. Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.
The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An interrupt is generated when: 1. 2. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC is received. For Programmed I/O: a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. b. When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. When ackIntEn is 1 and the nAck signal transitions from a low to a high.
3. 4.
12.4.6 FIFO Operation
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.
12.5
DMA Transfers
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted,
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disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes inactive after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an unwanted cycle.)
12.5.1 Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
12.5.2 Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold = (16-) data bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO.
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If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16) bytes may be read from the FIFO in a single burst.
12.5.3 Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-) free bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO.
12.6
Parallel Port Floppy Disk Controller
In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in the Parallel Port Mode Register, as defined in the Parallel Port Mode Register, Logical Device 3, at 0xF1. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. When the PPFDC is selected the following pins are set as follows: 1. 2. 3. nPDACK: high-Z PDRQ: not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z PINTR: not active, this is hi-Z or Low depending on settings.
Note:
nPDACK, PDRQ and PINTR refer to the nDACK, DRQ and IRQ chosen for the parallel port. The following parallel port pins are read as follows by a read of the parallel port register: 1. 2. 3. Data Register (read) = last Data Register (write) Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1 Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1.
The following FDC pins are all in the high impedance state when the PPFDC is actually selected by the drive select register: 1. 2. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1. If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is selected.
The FDC signals are muxed onto the Parallel Port pins as shown in Table 12.8.
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Table 12.8 - FDC Parallel Port Pins CONNECTOR PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CHIP PIN # 83 68 69 70 71 72 73 74 75 80 79 78 77 82 81 66 67 SPP MODE nSTROBE PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nALF nERROR nINIT nSLCTIN PIN DIRECTION I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O FDC MODE (nDS0) nINDEX nTRK0 nWP nRDATA nDSKCHG nMEDIA_ID0 (nMTR0) MEDIA_ID1 nDS1 nMTR1 nWDATA nWGATE DRVDEN0 nHDSEL nDIR nSTEP PIN DIRECTION I/(O) Note 12.10 I I I I I I I/(O) Note 12.10 I O O O O O O O O
Note 12.10 These pins are outputs in mode PPFD2, inputs in mode PPFD1.
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Chapter 13 Auto Power Management
Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B0. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met: 1. 2. 3. 4. The motor enable pins of register 3F2H are inactive (zero). The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The head unload timer must have expired. The Auto powerdown timer (10msec) must have timed out.
An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown. DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the RESET pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1. 2. 3. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). A read from the MSR register. A read or write to the Data register.
Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. Register Behavior Table 13.1 reiterates the AT and PS/2 (including Model 30) configuration registers available. It also shows the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 13.1 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it.
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Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed. Pin Behavior The FDC37C672 is specifically designed for portable PC systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the FDC37C672 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part. System Interface Pins Table 12.8 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Input pins are "Disabled" to prevent them from causing currents internal to the FDC37C672 when they have indeterminate input values.
Table 13.1 - PC/AT and PS/2 Available Registers BASE + ADDRESS AVAILABLE REGISTERS ACCESS PERMITTED PC-AT PS/2 (MODEL 30) Access to these registers DOES NOT wake up the part ---SRA R ---SRB R DOR (Note 13.1) DOR (Note 13.1) R/W ------DSR (Note 13.1) DSR (Note 13.1) W ------DIR DIR R CCR CCR W Access to these registers wakes up the part MSR MSR R Data Data R/W
00H 01H 02H 03H 04H 06H 07H 07H 04H 05H
Note 13.1 Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part
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Table 13.2 - State of System Pins in Auto Powerdown SYSTEM PINS STATE IN AUTO POWERDOWN INPUT PINS nIOR Unchanged nIOW Unchanged SA[0:9] Unchanged SD[0:7] Unchanged RESET_DRV Unchanged DACKx Unchanged TC Unchanged Output Pins IRQx Unchanged (low) SD[0:7] Unchanged DRQx Unchanged (low) FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 13.3 depicts the state of the floppy disk drive interface pins in the powerdown state.
Table 13.3 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins nRDATA nWPROT nTR0 nINDEX nDSKCHG Output Pins nMTR[0:1] nDS[0:1] nDIR nSTEP nWDATA nWGATE nHDSEL DRVDEN[0:1] UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations:
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State in Auto Powerdown Input Pins Input Input Input Input Input Tristated Tristated Active Active Tristated Tristated Active Active
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1. 2.
The transmitter enters auto powerdown when the transmit buffer and shift register are empty. The receiver enters powerdown when the following conditions are all met: a. Receive FIFO is empty b. The receiver is waiting for a start bit.
Note:
While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes. Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state. Parallel Port Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any of the following conditions: 1. 2. EPP is not enabled in the configuration registers. EPP is not selected through ecr while in ECP mode.
The ECP logic is in powerdown under any of the following conditions: 1. 2. ECP is not enabled in the configuration registers. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.
Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.
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Chapter 14 Serial IRQ
The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the SMI pin via bit 7 of the SMI Enable Register 2.
14.1
Serial Interrupts
The FDC37C672 will support the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
14.1.1 Timing Diagrams For IRQSER Cycle
PCICLK = 33Mhz_IN pin IRQSER = SIRQ pin A. Start Frame timing with source sampled a low pulse on IRQ1
SL
or
START FRAME H R T
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T
H PCICLK IRQSER Drive Source IRQ1
START1 Host Controller None
R=Recovery T=Turn-around
IRQ1
None
H=Host Control SL=Slave Control S=Sample Note1: Start Frame pulse can be 4-8 clocks wide.
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B.
Stop Frame Timing with Host using 17 IRQSER sampling period
IRQ14 FRAME SRT PCICLK IRQSER Driver None
IRQ15 FRAME SRT
IOCHCK# FRAME SRT
STOP FRAME
NEXT CYCLE T
I
2
H
R
STOP1 IRQ15 None Host Controller
START3
H=Host Control T=Turn-around R=Recovery S=Sample I= Idle. Note 1 Note 2 Note 3 Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. There may be none, one or more Idle states during the Stop Frame. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame.
14.1.2 IRQSER Cycle Control
There are two modes of operation for the IRQSER Start Frame. 1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the IRQSER low for one clock, while the IRQSER is Idle. After driving low for one clock the IRQSER must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the IRQSER is Active. The IRQSER is Idle between Stop and Start Frames. The IRQSER is Active between Start and Stop Frames. This mode of operation allows the IRQSER to be Idle when there are no IRQ/Data transitions which should be most of the time. Once a Start Frame has been initiated the Host Controller will take over driving the IRQSER low in the next clock and will continue driving the IRQSER low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the IRQSER back high for one clock, then tri-state. Any IRQSER Device (i.e., The FDC37C672) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the IRQSER is already in an IRQSER Cycle and the IRQ/Data transition can be delivered in that IRQSER Cycle. 2. Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other IRQSER agents become passive and may not initiate a Start Frame. IRQSER will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the IRQSER or the Host Controller can operate IRQSER in a continuous mode by initiating a Start Frame at the end of every Stop Frame. An IRQSER mode transition can only occur during the Stop Frame. Upon reset, IRQSER bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next IRQSER Cycle's mode.
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14.1.3 IRQSER Data Frame
Once a Start Frame has been initiated, the FDC37C672 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the FDC37C672 must drive the IRQSER (SIRQ pin) low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, IRQSER must be left tri-stated. During the Recovery phase the FDC37C672 must drive the SERIRQ high, if and only if, it had driven the IRQSER low during the previous Sample Phase. During the Turn-around Phase the FDC37C672 must tri-state the SERIRQ. The FDC37C672 will drive the IRQSER line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g.: The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse.) Table 14.1 - IRQSER Sampling Periods IRQSER PERIOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SIGNAL SAMPLED Not Used IRQ1 nSMI/IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 # OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47
The SIRQ data frame will now support IRQ2 from a logical device, previously IRQSER Period 3 was reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. IRQSER Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), 6 (RTC), and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt.
14.1.4 Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low for two or three clocks. If the Stop Frame's low time is two clocks then the next IRQSER Cycle's sampled mode is the Quiet mode; and any IRQSER device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. If the Stop Frame's low time is three clocks then the next IRQSER Cycle's sampled mode is the Continuous mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse.
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14.1.5 Latency
Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
14.1.6 EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the IRQSER Cycle latency in order to ensure that these events do not occur out of order.
14.1.7 AC/DC Specification Issue
All IRQSER agents must drive / sample IRQSER synchronously related to the rising edge of PCI bus clock. IRQSER (SIRQ) pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state.
14.1.8 Reset and Initialization
The IRQSER bus uses RESET_DRV as its reset signal. The IRQSER pin is tri-stated by all agents while RESET_DRV is active. With reset, IRQSER Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial IRQSER Cycle to collect system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent IRQSER Cycles. It is Host Controller's responsibility to provide the default values to 8259's and other system logic before the first IRQSER Cycle is performed. For IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee IRQSER bus is in IDLE state before the system configuration changes.
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Chapter 15 GP Index Registers
The Watchdog Timer Control, SMI Enable and SMI Status Registers can be accessed by the host when the chip is in the normal run mode if CR03 Bit[7]=1. The host uses GP Index and Data register to access these registers. The Power on default GP Index and Data registers are 0xEA and 0xEB respectively. In configuration mode the GP Index address may be programmed to reside on addresses 0xE0, 0xE2, 0xE4 or 0xEA. The GP Data address is automatically set to the Index address + 1. Upon exiting the configuration mode the new GP Index and Data registers are used to access registers WDT_CTRL, SMI Enable and SMI Status Registers. To access these registers when in normal (run) mode, the host should perform an IOW of the Register Index to the GP Index register (at 0xEX) to select the Register and then read or write the Data register (at Index+1) to access the register. The WDT_CTRL, SMI Enable and SMI Status registers can also be accessed by the host when in the configuration state through Logical Device 8.
Table 15.1 - GP Index and Data Register REGISTER GP Index GP Data ADDRESS (R/W) 0xE0, E2, E4, EA Index address + 1 NORMAL (RUN) MODE 0x01-0x0F Access to Watchdog Timer Control, SMI Enable and SMI Status Registers (see Table 15.2)
Table 15.2- Index and Data Register Normal (Run) Mode INDEX 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Note: NORMAL (RUN) MODE Reserved Reserved Access to Watchdog Timer Control (L8 - CRF4) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Access to SMI Enable Register 1 (L8-CRB4) Access to SMI Enable Register 2 (L8-CRB5) Access to SMI Status Register 1 (L8-CRB6) Access to SMI Status Register 2 (L8-CRB7)
These registers can also be accessed through the configuration registers at L8 - CRxx shown in the table above.
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Chapter 16 Watch Dog Timer
The FDC37C672 contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt through the WDT_CFG Configuration Register. The FDC37C672's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the WDT_TIMEOUT register (LD8:CRF1.7). The WDT time-out value is set through the WDT_VAL Configuration register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Configuration Register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU. There are three system events which can reset the WDT, these are a Keyboard Interrupt, a Mouse Interrupt, or I/O reads/writes to address 0x201 (the internal or an external Joystick Port). The effect on the WDT for each of these system events may be individually enabled or disabled through bits in the WDT_CFG configuration register. When a system event is enabled through the WDT_CFG register, the occurrence of that event will cause the WDT to reload the value stored in WDT_VAL and reset the WDT time-out status bit if set. If all three system events are disabled the WDT will inevitably time out. The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Configuration Register. When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit. The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Configuration Register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing.
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Chapter 17 8042 Keyboard Controller Description
The FDC37C672 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Super I/O supports a Floppy Disk Controller, two 16550 type serial ports one ECP/EPP Parallel Port. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the FDC37C672 enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" in the 8-Bit Embedded Controller Handbook.
8042A
P27 P10 P26 TST0 P23 TST1 P22 P11
LS05 KDAT KCLK MCLK MDAT
Figure 17.1 - Keyboard and Mouse Interface Notes: KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the FDC37C672.
17.1
Keyboard ISA Interface
The FDC37C672 ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, Input Data register, and Output Data register. Table 17.1 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs.
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Table 17.1 - ISA I/O Address Map ISA ADDRESS 0x60 0x64 NIOW 0 1 0 1 NIOR 1 0 1 0 BLOCK KDATA KDATA KDCTL KDCTL FUNCTION (Note 17.1) Keyboard Data Write (C/D=0) Keyboard Data Read Keyboard Command Write (C/D=1) Keyboard Status Read
Note 17.1 These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read.
17.1.1 Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set.
17.1.2 Keyboard Data Read
This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
17.1.3 Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set.
17.1.4 Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
17.1.5 CPU-to-Host Communication
The FDC37C672 CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 17.2.
Table 17.2 - Host Interface Flags 8042 INSTRUCTION OUT DBB FLAG Set OBF, and, if enabled, the KIRQ output signal goes high
17.1.6 Host-to-CPU Communication
The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
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17.1.7 KIRQ
If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the FDC37C672 CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.) If "EN FLAGS" has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low; a high forces KIRQ high.
17.1.8 MIRQ
If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the FDC37C672 CPU has read the DBB register. If "EN FLAGS" has not been executed, MIRQ is controlled by P25. Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support.)
17.1.9 Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
17.2
External Keyboard and Mouse Interface
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the FDC37C672 provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse.
The FDC37C672 has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as ISA external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11.
Note:
External pull-ups may be required.
17.3
Keyboard Power Management
The keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped.
17.3.1 Soft Power Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with
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a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution starts from program memory location 0.
17.3.2 Hard Power Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
17.4
Interrupts
The FDC37C672 provides the two 8042 interrupts. IBF and the Timer/Counter Overflow.
17.5
Memory Configurations
The FDC37C672 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
17.5.1 Register Definitions
Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. Host I/F Status Register The Status register is 8 bits wide. Table 17.3 shows the contents of the Status register. Table 17.3 - Status Register D7 UD D6 UD D5 UD D4 UD D3 C/D D2 UD D1 IBF D0 OBF
17.5.2 Status Register
This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37C672 CPU. UD C/D Writable by FDC37C672 CPU. These bits are user-definable. (Command Data) -This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. (Input Buffer Full) - This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the FDC37C672 CPU's nIBF (MIRQ) interrupt if enabled.
IBF
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When the FDC37C672 CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. OBF (Output Buffer Full) - This flag is set to whenever the FDC37C672 CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset.
17.6
External Clock Signal
The FDC37C672 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 Mhz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
17.7
Default Reset Conditions
The FDC37C672 has one source of reset: an external reset via the RESET_DRV pin. Refer to Table 17.4 for the effect of each type of reset on the internal registers.
Table 17.4 - Resets DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Host I/F Status Reg Note: N/A: Not Applicable HARDWARE RESET (RESET) Weak High Weak High Weak High Weak High N/A 00H
17.8
GATEA20 and Keyboard Reset
The FDC37C672 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
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17.9
Port 92 Fast GATEA20 and Keyboard Reset
17.9.1 Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1. This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions. Name Location Default Value Attribute Size Port 92 92h 24h Read/Write 8 bits
PORT 92 REGISTER BIT 7:6 5 4 3 2 1 FUNCTION Reserved. Returns 00 when read. Reserved. Returns a 1 when read. Reserved. Returns a 0 when read. Reserved. Returns a 0 when read. Reserved. Returns a 1 when read. ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high. Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0. NGATEA20 8042 P21 0 0 1 1 ALT_A20 0 1 0 1 SYSTEM NA20M 0 1 1 1
0
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND'ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
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If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is AND'ed with the pulse generated from the 8042. This pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.
14us
~ ~
6us
8042
P20
KRST
P92 Bit 0
KRST_GA20 Bit 2 nALT_RST Pulse Gen
14us
KBDRST
Note: When Port 92 is disabled, writes are ignored and reads return undefined values.
KRESET Generation
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR'ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low.
~ ~
6us
17.9.2 8042 P12 and P16 Functions
8042 functions P12 and P16 are implemented as in a true 8042 part. Reference the 8042 spec for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within 20-30nsec. After several (# TBD) clocks, the port enable goes away and the internal 90A pull-up maintains the output signal as 1. In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared i.e., P12 and nSMI can be externally tied together. In 8042 mode, the pins cannot be programmed as input nor inverted through the GP configuration registers.
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0ns CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20
250ns
500ns
Figure 17.2 - Gate A20 Turn-On Sequence Timing
When writing to the command and data port with hardware speedup, the IOW timing shown in the figure titled "IOW Timing for Port 92" in the Timing Diagrams Section is used. This setup time is only required to be met when using hardware speedup; the data must be valid a minimum of 0 nsec from the leading edge of the write and held throughout the entire write cycle.
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Chapter 18 System Management Interrupt (SMI)
The FDC37C672 implements a group nSMI output pin. The System Management Interrupt is a nonmaskable interrupt with the highest priority level used for transparent power management. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The nSMI output is then enabled onto the group nSMI output pin via bit[7] in the SMI Enable Register 2. The logic equation for the nSMI output is as follows: nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT)
18.1
Registers
The following registers can be accessed when in configuration mode at Logical Device 8, Registers B4-B7 and when not in configuration they can be accessed through the Index and Data Register (refer to Table 15.2).
18.1.1 SMI Enable Registers
SMI Enable Register 1 (Configuration Register B4, Logical Device 8) This register is used to enable the different interrupt sources onto the group nSMI output. SMI Enable Register 2 (Configuration Register B5, Logical Device 8) This register is used to enable additional interrupt sources onto the group nSMI output. This register is also used to enable the group nSMI output onto the nSMI Serial/Parallel IRQ pin and the routing of 8042 P12 internally to nSMI.
18.1.2 SMI Status Registers
SMI Status Register 1 (Configuration Register B6, Logical Device 8) This register is used to read the status of the SMI input events. Note: The status bit gets set whether or not the interrupt is enabled onto the group SMI output. SMI Status Register 2 (Configuration Register B7, Logical Device 8)
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Chapter 19 Configuration
The Configuration of the FDC37C672 is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The FDC37C672 is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the FDC37C672 allows the BIOS to assign resources at POST.
19.1
System Elements
19.1.1 Primary Configuration Address Decoder
After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37C672 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the FDC37C672 into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the FDC37C672 is in Configuration Mode. The SYSOPT pin is latched on the falling edge of the RESET_DRV or on Vcc Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG PORT's I/O address at power-up. Once powered up the configuration port base address can be changed through configuration registers CR26 and CR27. The SYSOPT pin is a hardware configuration pin which is shared with the nRTS1 signal on pin 87. During reset this pin is a weak active low signal which sinks 30A. Note: All I/O addresses are qualified with AEN. The INDEX and DATA ports are effective only when the chip is in the Configuration State. PORT NAME CONFIG PORT (Note 19.2) INDEX PORT (Note 19.2) DATA PORT SYSOPT= 0 (PULL-DOWN RESISTOR) REFER TO Note 19.1 0x03F0 0x03F0 INDEX PORT + 1 SYSOPT= 1 (10K PULL-UP RESISTOR) 0x0370 0x0370 TYPE Write Read/Write Read/Write
Note 19.1 If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use 10K pull-down. Note 19.2 The configuration port base address can be relocated through CR26 and CR27.
19.1.2 Entering the Configuration State
The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0x55 >
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19.1.3 Exiting the Configuration State
The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0xAA>
19.2
Configuration Sequence
To program the configuration registers, the following sequence must be followed: 1. 2. 3. Enter Configuration Mode Configure the Configuration Registers Exit Configuration Mode.
19.2.1 Enter Configuration Mode
To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State. (The auto Config ports are enabled.)
19.2.2 Configuration Mode
The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: a. b. Note: Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT.
If accessing the Global Configuration Registers, step (a) is not required.
19.2.3 Exit Configuration Mode
To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State.
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19.2.4 Programming Example
The following is an example of a configuration program in Intel 8086 assembly language. ;--------------------------------------------------. ; ENTER CONFIGURATION MODE | ;--------------------------------------------------' MOV DX,3F0H MOV AX,055H OUT DX,AL ;--------------------------------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;--------------------------------------------------' MOV DX,3F0H MOV AL,07H OUT DX,AL ; Point to LD# Config Reg MOV DX,3F1H MOV AL, 08H OUT DX,AL ; Point to Logical Device 8 ; MOV DX,3F0H MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,3F1H MOV AL,02H OUT DX,AL ; Update CRE0 ;-------------------------------------------------. ; EXIT CONFIGURATION MODE | ;-------------------------------------------------' MOV DX,3F0H MOV AX,0AAH OUT DX,AL Notes: 1. 2. 3. HARD RESET: RESET_DRV pin asserted SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500s after Vcc POR (see Power-up Timing Diagram) Table 19.1 - Configuration Registers INDEX 0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26 0x27 TYPE W R/W R/W R R R/W R/W R/W R/W R/W HARD RESET VCC POR SOFT RESET CONFIGURATION REGISTER GLOBAL CONFIGURATION REGISTERS 0x00 Config Control 0x03 Index Address 0x00 0x00 Logical Device Number 0x40 Device ID - hard wired Current Revision Device Rev - hard wired 0x00 0x00 Power Control 0x00 Power Mgmt 0x04 OSC Sysopt=0: 0xF0 Configuration Port Address Byte 0 Sysopt=1: 0x70 Sysopt=0: 0x03 Configuration Port Address Byte 1 Sysopt=1: 0x03
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INDEX 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF5
TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0x30 0x60, 0x61 0x70 0xF0 0x30 0x60, 0x61 0x62, 0x63 0x70 0x74 0xF0 0xF1 0xF2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x30 0x70
R/W R/W
HARD RESET VCC POR SOFT RESET CONFIGURATION REGISTER 0x00 TEST 4 0x00 TEST 5 0x00 TEST 1 0x00 TEST 2 0x00 TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 0x00 0x00 Activate 0x03, 0x03,0xF0 Primary Base I/O Address 0xF0 0x06 0x06 Primary Interrupt Select 0x02 0x02 DMA Channel Select 0x0E FDD Mode Register 0x00 FDD Option Register 0xFF FDD Type Register 0x00 FDD0 0x00 FDD1 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x00 0x00 Activate 0x00, 0x00,0x00 Primary Base I/O Address 0x00 0x00 0x00 Primary Interrupt Select 0x04 0x04 DMA Channel Select 0x3C Parallel Port Mode Register 0x00 Parallel Port Mode Register 2 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 0x00 0x00 Activate 0x00, 0x00,0x00 Primary Base I/O Address 0x00 0x00 0x00 Primary Interrupt Select 0x00 Serial Port 1 Mode Register LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) 0x00 0x00 Activate 0x00, 0x00,0x00 Primary Base I/O Address 0x00 0x00, 0x00,0x00 Fast IR Base I/O Address 0x00 0x00 0x00 Primary Interrupt Select 0x04 0x04 DMA Channel Select 0x00 Serial Port 2 Mode Register 0x02 IR Options Register 0x03 IR Half Duplex Timeout LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard) 0x00 0x00 Activate 0x00 0x00 Primary Interrupt Select
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INDEX 0x72 0xF0 0x30 0xB4 0xB5 0xB6 0xB7 0xC0 0xC1 0xC2 0xC3 0xC4 0xF1 0xF2 0xF3 0xF4 0xF6 : FB
TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W Note 19.3
HARD RESET VCC POR SOFT RESET CONFIGURATION REGISTER 0x00 0x00 Second Interrupt Select 0x00 KRESET and GateA20 Select LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 0x00 0x00 Activate 0x00 SMI Enable Register 1 0x00 SMI Enable Register 2 0x00 SMI Status Register 1 0x00 SMI Status Register 2 0x06 Pin Multiplex Controls 0x03 Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow UART2 FIFO Control Shadow 0x00 WDT_TIME_OUT 0x00 WDT_VAL 0x00 WDT_CFG 0x00 WDT_CTRL
Reserved LOGICAL DEVICE 9 CONFIGURATION REGISTERS (RESERVED)
Note 19.3 This register contains some bits which are read or write only.
19.2.5 Chip Level (Global) Control/Configuration Registers [0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode.
Table 19.2 - Chip Level Registers REGISTER ADDRESS 0x00 -0x01 0x02 W DESCRIPTION Chip (Global) Control Registers Reserved - Writes are ignored, reads return 0. The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit 0 = 1: Soft Reset. Refer to the "Configuration Registers" table for the soft reset value for each register. STATE
Config Control Default = 0x00 on Vcc POR or Reset_Drv
C
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REGISTER Index Address Default = 0x03 on Vcc POR or Reset_Drv
ADDRESS 0x03 R/W
DESCRIPTION Bit[7] = 1 Enable WDT_CTRL and SMI Enable and SMI Status Register access when not in configuration mode = 0 Disable WDT_CTRL and SMI Enable and SMI Status Register access when not in configuration mode (Default) Bits [6:2] Reserved - Writes are ignored, reads return 0. Bits[1:0] Sets GP index register address when in Run mode (not in Configuration Mode). = 11 0xEA (Default) = 10 0xE4 = 01 0xE2 = 00 0xE0 Reserved - Writes are ignored, reads return 0. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device.
STATE
0x04 - 0x06 Logical Device # Default = 0x00 on Vcc POR or Reset_Drv Card Level Reserved Device ID Hard wired = 0x40 Device Rev Hard wired = 0x01 PowerControl Default = 0x00. on Vcc POR or Reset_Drv hardware signal 0x08 - 0x1F 0x20 R 0x07 R/W
C
Reserved - Writes are ignored, reads return 0. Chip Level, SMSC Defined A read only register which provides device identification. Bits[7:0] = 0x40 when read.
C
0x21 R
A read only register which provides device revision information. Bits[7:0] = 0x01 when read.
C
0x22 R/W
Bit[0] FDC Power Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] Reserved Bit[7] Reserved (read as 0) = 0 Power off or disabled = 1 Power on or enabled
C
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REGISTER Power Mgmt Default = 0x00. on Vcc POR or Reset_Drv hardware signal
ADDRESS 0x23 R/W
DESCRIPTION Bit[0] FDC Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[6:7] Reserved (read as 0) = 0 Intelligent Pwr Mgmt off = 1 Intelligent Pwr Mgmt on Bit[0] Reserved Bit [1] PLL Control = 0 PLL is on (backward Compatible) = 1 PLL is off Bits[3:2] OSC = 01 Osc is on, BRG clock is on. = 10 Same as above (01) case. = 00 Osc is on, BRG Clock Enabled. = 11 Osc is off, BRG clock is disabled. Bit [5:4] Reserved, set to zero Bit [6] 16-Bit Address Qualification = 0 12-Bit Address Qualification = 1 16-Bit Address Qualification Bit[7] Reserved Reserved - Writes are ignored, reads return 0. Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 See Note 19.4
STATE C
OSC Default = 0x04, on Vcc POR or Reset_Drv hardware signal.
0x24 R/W
C
Chip Level Vendor Defined Configuration Address Byte 0 Default =0xF0 (Sysopt=0) =0x70 (Sysopt=1) on Vcc POR or Reset_Drv Configuration Address Byte 1 Default = 0x03 on Vcc POR or Reset_Drv Default = 0x00 on VCC POR and Hard Reset Chip Level Vendor Defined TEST 4 Default = 0x00, on Vcc POR
0x25 0x26
C
0x27
Bit[7:0] Configuration Address Bits [15:8] See Note 19.4
C
0x28
Bits[7:0] Reserved - Writes are ignored, reads return 0.
0x29 -0x2A 0x2B R/W
Reserved - Writes are ignored, reads return 0. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. C
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REGISTER TEST 5 Default = 0x00, on Vcc POR TEST 1 Default = 0x00, on Vcc POR TEST 2 Default = 0x00, on Vcc POR TEST 3 Default = 0x00, on Vcc POR
ADDRESS 0x2C R/W
DESCRIPTION Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
STATE C
0x2D R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
0x2E R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
0x2F R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
C
Note 19.4 To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address). The configuration address is only reset to its default address upon a Hard Reset or Vcc POR. Note: The default configuration address is either 3F0 or 370, as specified by the SYSOPT pin. This change affects SMSC Mode only.
19.2.6 Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard Controller, and Auxiliary_I/O. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below. Table 19.3 - Logical Device Registers LOGICAL DEVICE REGISTER Activate (Note 19.5) Default = 0x00 on Vcc POR or Reset_Drv Logical Device Control
SMSC FDC37C672
ADDRESS (0x30)
DESCRIPTION Bits[7:1] Reserved, set to zero. Bit[0] = 1 Activates the logical device currently selected through the Logical Device # register. = 0 Logical device currently selected is inactive Reserved - Writes are ignored, reads return 0.
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STATE C
(0x31-0x37)
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LOGICAL DEVICE REGISTER Logical Device Control Memory Base Address I/O Base Address (see Device Base I/O Address Table) Default = 0x00 on Vcc POR or Reset_Drv Interrupt Select Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv
ADDRESS (0x38-0x3f) (0x40-0x5F) (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] (0x70,0x72)
DESCRIPTION Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 19.12 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible).
STATE C C C
C
(0x71,0x73) DMA Channel Select Default = 0x04 on Vcc POR or Reset_Drv 32-Bit Memory Space Configuration Logical Device Logical Device Configuration Reserved (0x74,0x75)
Reserved - not implemented. These register locations ignore writes and return zero when read. Only 0x74 is implemented for FDC, Serial Port 2 and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to DMA Channel Configuration. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - Vendor Defined (see SMSC defined Logical Device Configuration Registers). Reserved
C
(0x76-0xA8) (0xA9-0xDF) (0xE0-0xFE) 0xFF
C C C
Note 19.5 A logical device will be active and powered up according to the following equation: DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored.
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Table 19.4 - I/O Base Address Configuration Register Description LOGICAL DEVICE NUMBER 0x00 LOGICAL DEVICE FDC REGISTER INDEX 0x60,0x61 BASE I/O RANGE (Note 19.6) [0x100:0x0FF8] ON 8 BYTE BOUNDARIES FIXED BASE OFFSETS +0 : SRA +1 : SRB +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR +0 : Data|ecpAfifo +1 : Status +2 : Control +3 : EPP Address +4 : EPP Data 0 +5 : EPP Data 1 +6 : EPP Data 2 +7 : EPP Data 3 +400h : cfifo|ecpDfifo|tfifo |cnfgA +401h : cnfgB +402h : ecr +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : Fast IR Registers +1 : Fast IR Registers +2 : Fast IR Registers +3 : Fast IR Registers +4 : Fast IR Registers +5 : Fast IR Registers +6 : Fast IR Registers +7 : Fast IR Registers +0 : Data Register +4 : Command/Status Reg.
0x03
Parallel Port
0x60,0x61
[0x100:0x0FFC] ON 4 BYTE BOUNDARIES (EPP Not supported) or [0x100:0x0FF8] ON 8 BYTE BOUNDARIES (all modes supported, EPP is only available when the base address is on an 8-byte boundary) [0x100:0x0FF8] ON 8 BYTE BOUNDARIES
0x04
Serial Port 1
0x60,0x61
0x05
Serial Port 2
0x60,0x61
[0x100:0x0FF8] ON 8 BYTE BOUNDARIES
0x62,0x63
[0x100:0x0FF8] ON 8 BYTE BOUNDARIES
0x06 0x07 0x09
SMSC FDC37C672
Reserved KYBD Reserved
n/a
Not Relocatable Fixed Base Address: 60,64
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Note 19.6 This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices.
Table 19.5 - Interrupt Select Configuration Register Description NAME Interrupt Request Level Select 0 Default = 0x00 on Vcc POR or Reset_Drv REG INDEX 0x70 (R/W) DEFINITION Bits[3:0] selects which interrupt level is used for Interrupt 0. 0x00= no interrupt selected. 0x01= IRQ1 0x02= IRQ2/nSMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ6 0x06= IRQ7 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Notes: All interrupts are edge high (except ECP/EPP) nSMI is active low Notes: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND: for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. for the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. for the RTC by (refer to the RTC section of this spec.) for the KYBD by (refer to the KYBD controller section of this spec.) IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Section 19.2.7 - Note A. Logical Device IRQ and DMA Operation. nSMI must be disabled to use IRQ2. All IRQ's are available in Serial IRQ mode. Only IRQ[3:7] and IRQ[10:12] are available in Parallel IRQ mode. STATE C
Table 19.6 - DMA Channel Select Configuration Register Description NAME DMA Channel Select Default = 0x04 on Vcc POR or Reset_Drv REG INDEX 0x74 (R/W) DEFINITION Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active STATE C
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Notes: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. for the UART 2 logical device, by setting the DMA Enable bit. Refer to the IRCC specification. DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Section 19.2.7 - Note A. Logical Device IRQ and DMA Operation.
19.2.7 Note A. Logical Device IRQ and DMA Operation
1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the IRQ and DACK disabled by the Configuration Registers (active bit or address not valid). a. FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high impedance). Will not respond to the DREQ Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". The FDC is in power down (disabled). b. Serial Port 1 and 2: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is forced to a high impedance state - disabled. c. Parallel Port: i. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled (high impedance). ii. ECP Mode: (1) (DMA) dmaEn from ecr register. See table. (2) IRQ - See table. MODE IRQ PIN PDREQ PIN (FROM ECR REGISTER) CONTROLLED BY CONTROLLED BY 000 PRINTER IRQE dmaEn 001 SPP IRQE dmaEn 010 FIFO (on) dmaEn 011 ECP (on) dmaEn 100 EPP IRQE dmaEn 101 RES IRQE dmaEn 110 TEST (on) dmaEn 111 CONFIG IRQE dmaEn d. Keyboard Controller: Refer to the KBD section of this spec.
19.2.8 SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the RESET_DRV signal. These registers are not affected by soft resets.
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Table 19.7 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME FDD Mode Register Default = 0x0E on Vcc POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[0] Floppy Mode = 0 Normal Floppy Mode (default) = 1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] Swap Drives 0,1 Mode = 0 No swap (default) = 1 Drive and Motor sel 0 and 1 are swapped. Bit[5] Reserved, set to zero Bit[6] FDC Output Type Control = 0 FDC outputs are OD24 open drain (default) = 1 FDC outputs are O24 push-pull Bit[7] FDC Output Control = 0 FDC outputs active (default) = 1 FDC outputs tri-stated Note: Bits 6 & 7 do not affect the parallel port FDC pins. FDD Option Register Default = 0x00 on Vcc POR or Reset_Drv 0xF1 R/W Bits[1:0] Reserved, set to zero Bits[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[4] Media ID 0 Polarity = 0: Don't invert (default) = 1: Invert Bit[5] Media ID 1 Polarity = 0: Don't invert (default) = 1: Invert Bits[7:6] Boot Floppy = 00 FDD 0 (default) = 01 FDD 1 = 10 Reserved (neither drive A or B is a boot drive). = 11 Reserved (neither drive A or B is a boot drive). Bits[1:0] Floppy Drive A Type Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The FDC37C672 supports two floppy drives 0xF3 R
SMSC FDC37C672
STATE C
C
FDD Type Register Default = 0xFF on Vcc POR or Reset_Drv
0xF2 R/W
C
Reserved, Read as 0 (read only)
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NAME FDD0 Default = 0x00 on Vcc POR or Reset_Drv
REG INDEX 0xF4 R/W
FDD1
0xF5 R/W
DEFINITION Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) Bits[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bits[7] Read as 0 (read only) Refer to definition and default for 0xF4
STATE C
C
Table 19.8 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME PP Mode Register Default = 0x3C on Vcc POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interrupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). =1 Pulsed Low, released to high-Z. =0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. Bits[1:0] PPFDC - muxed PP/FDC control = 00 Normal Parallel Port Mode = 01 PPFD1: Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins Drive 2 is on the FDC pins Drive 3 is on the FDC pins = 10 PPFD2: Drive 0 is on the Parallel port pins Drive 1 is on the Parallel port pins Drive 2 is on the FDC pins Drive 3 is on the FDC pins Bits[7:2] Reserved. Set to zero. STATE C
PP Mode Register 2 Default = 0x00 on Vcc POR or Reset_Drv
0xF1 R/W
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Table 19.9 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME Serial Port 1 Mode Register Default = 0x00 on Vcc POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed Disabled(default) = 1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7]: Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note 19.7 below. Note 19.7 To properly share and IRQ, 1. Configure UART1 (or UART2) to use the desired IRQ pin. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note: If both UARTs are configured to use different IRQ pins and the share IRQ bit is set, then both of the UART IRQ pins will assert when either UART generates an interrupt. STATE C
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Table 19.10 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME Serial Port 2 Mode Register Default = 0x00 on Vcc POR or Reset_Drv IR Option Register Default = 0x02 on Vcc POR or Reset_Drv 0xF1 R/W REG INDEX 0xF0 R/W DEFINITION Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed disabled(default) = 1 High Speed enabled Bit[7:2] Reserved, set to zero Bit[0] Receive Polarity =0 Active High (Default) =1 Active Low Bit[1] Transmit Polarity =0 Active High =1 Active Low (Default) Bit[2] Duplex Select =0 Full Duplex (Default) =1 Half Duplex Bits[5:3] IR Mode = 000 Standard (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] IR Location Mux =0 Use Serial port TX2 and RX2 (Default) =1 Use alternate IRRX (pin 61) and IRTX (pin 62) Bit[7] Reserved, write 0. Bits [7:0] These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec ... STATE C
C
IR Half Duplex Timeout Default = 0x03 on Vcc POR or Reset_Drv
0xF2
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Table 19.11 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME KRST_GA20 Default = 0x00 on Vcc POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION KRESET and GateA20 Select Bit[7] Polarity Select for P12 = 0 P12 active low (default) = 1 P12 active high Bits[6:3] Reserved Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] Reserved Bit[0] Reserved Reserved - read as `0' STATE
0xF1 0xFF
Table 19.12 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME SMI Enable Register 1 Default = 0x00 on Vcc POR REG INDEX 0xB4 R/W DEFINITION This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] Reserved Bit[1] EN_PINT Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] EN_FINT Bit[5] Reserved Bit[6] Reserved Bit[7] EN_WDT This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nSMI GPI/O pin. Unless otherwise noted, 1=Enable 0=Disable Bit[0] EN_MINT Bit[1] EN_KINT Bit[2] EN_IRINT Bit[3] Reserved Bit[4] EN_P12: Enable 8042 P1.2 to route internally to nSMI. 0=Do not route to nSMI, 1=Enable routing to nSMI. Bit[5] Reserved Bit[6] EN_SMI_S: Enables nSMI Interrupt onto Serial IRQ. Bit[7] EN_SMI_P: Enables nSMI Interrupt onto Parallel Interrupt Pin IRQ10. 0=SMI pin floats, 1=Output onto nSMI GPI/O pin. STATE C
SMI Enable Register 2 Default = 0x00 on Vcc POR
0xB5 R/W
C
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NAME SMI Status Register 1 Default = 0x00 on Vcc POR
REG INDEX 0xB6 R/W
DEFINITION This register is used to read the status of the SMI inputs. The following bits must be cleared at their source. Bit[0] Reserved Bit[1] PINT (Parallel Port Interrupt) Bit[2] U2INT (UART 2 Interrupt) Bit[3] U1INT (UART 1 Interrupt) Bit[4] FINT (Floppy Disk Controller Interrupt) Bit[5] Reserved Bit[6] Reserved Bit[7] WDT (Watch Dog Timer) This register is used to read the status of the SMI inputs. Bit[0] MINT: Mouse Interrupt. Cleared at source. Bit[1] KINT: Keyboard Interrupt. Cleared at source. Bit[2] IRINT: This bit is set by a transition on the IR pin (RDX2 or IRRX as selected in CR L5-F1-B6 i.e., after the MUX). Cleared by a read of this register. Bit[3] Reserved Bit[4] P12: 8042 P1.2. Cleared at source Bit[7:5] Reserved Bits[7:0] Reserved Bit[0] IR Mode Select Bit[1] DMA 3 Select Bit[2] Serial IRQ Select Bit[3] 8042 Select Bit[4] IRRX 3 Select Bit[5:7] Reserved Bit[0] Force Change 0 Bit[1] Force Change 1 Bit[7:2] Reserved Force Change[1:0] can be written to 1 but are not clearable by software. Force Change 1 is cleared on nSTEP and nDS1 Force Change 0 is cleared on nSTEP and nDS0 DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR (nDS1 AND Force Change 1) OR nDSKCHG Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] PRECOMP 0 Bit[3] PRECOMP 1 Bit[4] PRECOMP 2 Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset
STATE C
SMI Status Register 2 Default = 0x00 on Vcc POR
0xB7 R/W
C
Default = 0x00 on VTR POR Pin Multiplex Controls Default = 0x06 on Vcc POR
0xB8 R/W 0xC0
C
Force Disk Change Default = 0x03 on Vcc POR
0xC1 (R/W)
C,R
Floppy Data Rate Select Shadow
0xC2 (R)
C
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NAME UART1 FIFO Control Shadow
REG INDEX 0xC3
UART2 FIFO Control Shadow
0xC4
DEFINITION Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB)
STATE C
C
Table 19.13 - nRTS MUXING MUX CONTROLS PIN NAME nRTS2 16 BIT ADDRESS QUAL. (CR24.6) 0 0 1 1 SERIRQSEL (LD8:CRC0.2) 1 0 1 0 SELECTED FUNCTION nRTS2 (default) IRQ5 SA12 Reserved STATE OF UNCONNECTED INPUTS 0 -
Table 19.14 - nCTS2 MUXING MUX CONTROLS PIN NAME nCTS2 16 BIT ADDRESS QUAL. (CR24.6) 0 0 1 1 SERIRQSEL (LD8:CRC0.2) 1 0 1 0 SELECTED FUNCTION nCTS2 (default) IRQ6 SA13 Reserved STATE OF UNCONNECTED INPUTS 1 0 -
Table 19.15 - nDTR2 MUXING MUX CONTROLS PIN NAME nDTR2 16 BIT ADDRESS QUAL. (CR24.6) 0 0 1 1 SERIRQSEL (LD8:CRC0.2) 1 0 1 0 SELECTED FUNCTION nDTR2 (default) IRQ7 SA14 Reserved STATE OF UNCONNECTED INPUTS 0 -
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Table 19.16 - nDSR2 MUXING MUX CONTROLS PIN NAME nDSR2 16 BIT ADDRESS QUAL. (CR24.6) 0 0 1 1 SERIRQSEL (LD8:CRC0.2) 1 0 1 0 SELECTED FUNCTION nDSR2 (default) IRQ10 (Note 19.8) SA15 Reserved STATE OF UNCONNECTED INPUTS 1 0 -
Note 19.8 LD8:CRB5.7 controls the IRQ10/nSMI interrupt mux.
Table 19.17 - nDCD2 MUXING MUX CONTROLS PIN NAME nDCD2 8042COMSEL. (LD8:CRC0.3) 0 0 1 1 SERIRQSEL (LD8:CRC0.2) 1 0 1 0 SELECTED FUNCTION nDCD2 (default) IRQ11 P12 Reserved STATE OF UNCONNECTED INPUTS 1 -
Table 19.18 - nRI2 MUXING MUX CONTROLS PIN NAME nRI2 8042COMSEL. (LD8:CRC0.3) 0 0 1 1 SERIRQSEL (LD8:CRC0.2) 1 0 1 0 SELECTED FUNCTION nRI2 (default) IRQ12 P16 Reserved STATE OF UNCONNECTED INPUTS 1 -
Table 19.19 - DRQ3 MUXING PIN NAME DRQ3 MUX CONTROL DMA3SEL (LD8:CRC0.1) 1 0 SELECTED FUNCTION DRQ3 (default) P12 STATE OF UNCONNECTED INPUTS -
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Table 19.20 - nDACK3 MUXING PIN NAME nDACK3 MUX CONTROL DMA3SEL (LD8:CRC0.1) 1 0 SELECTED FUNCTION nDACK3 (default) P16 STATE OF UNCONNECTED INPUTS 1 -
Table 19.21 - SER_IRQ MUXING PIN NAME SER_IRQ MUX CONTROL SERIRQSEL (LD8:CRC0.2) 1 0 SELECTED FUNCTION SER_IRQ (default) IRQ3 STATE OF UNCONNECTED INPUTS 1 -
Table 19.22 - PCI_CLK MUXING PIN NAME PCI_CLK MUX CONTROL SERIRQSEL (LD8:CRC0.2) 1 0 SELECTED FUNCTION PCI_CLK (default) IRQ4 STATE OF UNCONNECTED INPUTS 1 -
Table 19.23 - DRVDEN1 MUXING MUX CONTROLS PIN NAME DRVDEN1 IRMODESEL (LD8:CRC0.0) 0 1 1 Note 19.9 IRRX3SEL Default (0). IRRX3SEL (LD8:CRC0.4) 0 1 SELECTED FUNCTION DRVDEN1 (default) IRMODE (Note 19.9) IRRX3 STATE OF UNCONNECTED INPUTS 0
Table 19.24 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME WDT_TIME_OUT Default = 0x00 on Vcc POR or Reset_Drv REG INDEX 0xF1 DEFINITION Bit[0] Reserved Bit[1] Reserved Bits[6:2] Reserved, = 00000 Bit[7] WDT Time-out Value Units Select = 0 Minutes (default) = 1 Seconds STATE C
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NAME WDT_VAL Default = 0x00 on Vcc POR or Reset_Drv
REG INDEX 0xF2
DEFINITION Watch-dog Timer Time-out Value Binary coded, units = minutes(default) or seconds, selectable via Bit[7] of Reg 0xF1, LD 8. 0x00 Time out disabled 0x01 Time-out = 1 minute (second) 0xFF Time-out = 255 minutes (seconds) Watch-dog timer Configuration Bit[0] Joy-stick Enable =1 WDT is reset upon an I/O read or write of the Game Port =0 WDT is not affected by I/O reads or writes to the Game Port. Bit[1] Keyboard Enable =1 WDT is reset upon a Keyboard interrupt. =0 WDT is not affected by Keyboard interrupts. Bit[2] Mouse Enable =1 WDT is reset upon a Mouse interrupt =0 WDT is not affected by Mouse interrupts. Bit[3] Reserved Bits[7:4] WDT Interrupt Mapping 1111 = IRQ15 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable Watch-dog timer Control Bit[0] Watch-dog Status Bit, R/W =1 WD timeout occurred =0 WD timer counting Bit[1] Reserved Bit[2] Force Timeout, W =1 Forces WD timeout event; this bit is self-clearing Bit[3] P20 Force Timeout Enable, R/W = 1 Allows rising edge of P20, from the Keyboard Controller, to force the WD timeout event. A WD timeout event may still be forced by setting the Force Timeout Bit, bit 2. = 0 P20 activity does not generate the WD timeout event. Note: The P20 signal will remain high for a minimum of 1us and can remain high indefinitely. Therefore, when P20 forced timeouts are enabled, a self-clearing edgedetect circuit is used to generate a signal which is ORed with the signal generated by the Force Timeout Bit. Bit[7:4] Reserved. Set to 0
STATE C
WDT_CFG Default = 0x00 on Vcc POR or Reset_Drv
0xF3
C
WDT_CTRL Default = 0x00 Cleared by VTR POR
0xF4
C
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Chapter 20 Operational Description
20.1 Maximum Guaranteed Ratings*
Operating Temperature Range .................................................................................................. 0oC to +70oC Storage Temperature Range .................................................................................................. -55o to +150oC Lead Temperature Range (soldering, 10 seconds)............................................................................. +325oC Positive Voltage on any pin, with respect to Ground.........................................................................Vcc+0.3V Negative Voltage on any pin, with respect to Ground ............................................................................ -0.3V Maximum Vcc............................................................................................................................................ +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
20.2
DC Electrical Characteristics
(TA = 0C - 70C, Vcc = +5 V 10%) SYMBOL MIN TYP MAX UNITS COMMENTS
PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level ICLK2 Input Buffer Input Level
VILI VIHI 2.0
0.8
V V
TTL Levels
VILIS VIHIS VHYS 2.2 250
0.8
V V mV
Schmitt Trigger Schmitt Trigger
VILCK VIHCK 2.2
0.4
V V
500
mV
VP-P
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PARAMETER Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage VBAT IBAT Standby Current Input Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage O8SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time O24 Type Buffer Low Output Level High Output Level Output Leakage O16SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
IIL IIH
-10 -10 2.4 3.0 250
+10 +10 4.0 1000 100
A A V nA nA
VIN = 0 VIN = VCC VCC=VSS=0 VCC=5V, VBAT=3V
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 4 mA IOH = -2 mA VIN = 0 to VCC (Note 20.1)
+10
A
VOL VOH IOL TRT TFL 2.4 -10 5 5
0.4
V V
IOL = 8 mA IOH = -8 mA VIN = 0 to VCC (Note 20.1)
+10
A ns ns
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 20.1)
+10
A
VOL VOH IOL TRT TFL 2.4 -10 5 5
0.4
V V
IOL = 16 mA IOH = -16 mA VIN = 0 to VCC (Note 20.1)
+10
A ns ns
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PARAMETER OD16P Type Buffer Low Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage OD48 Type Buffer Low Output Level Output Leakage OCLK2 Type Buffer Low Output Level High Output Level Output Leakage ChiProtect
(SLCT, PE, BUSY, nACK, nERROR)
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL IOL -10
0.4 +10
V A
IOL = 16 mA IOH = 90 A VIN = 0 to VCC (Note 20.1)
VOL IOL
0.4 +10
V A
IOL = 24 mA VIN = 0 to VCC (Note 20.1)
VOL IOL
0.4 +10
V A
IOL = 48 mA VIN = 0 to VCC (Note 20.1)
VOL VOH IOL IIL IIL IIL ICCI 4.5 70 3.5 -10
0.4
V V
IOL = 2 mA IOH = -2 mA VIN = 0 to VCC (Note 20.1) VCC = 0V VIN = 6V Max VCC = 0V VIN = 6V Max VCC = 0V VIN = 6V Max All outputs open.
+10 10 10 10 90
A A A A mA
Backdrive
(nSTROBE, nAUTOFD, nINIT, nSLCTIN)
Backdrive
(PD0-PD7)
Supply Current Active
Note 20.1 All output leakages are measured with the current pins in high impedance Note 20.2 Output leakage is measured with the low driving output off, either for a high level output or a high impedance state. Note 20.3 KBCLK, KBDATA, MCLK, MDATA contain 90uA min pull-ups.
CAPACITANCE TA = 25C; fc = 1MHz; VCC = 5V PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN LIMITS TYP MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground
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Chapter 21 Timing Diagrams
For the Timing Diagrams shown, the following capacitive loads are used. CAPACITANCE TOTAL (PF) 240 240 120 120 240 240 240 240 240 240 240 240 100 100 100 100 100 100 240 240 240 240 240 240 240 240 240
NAME SD[0:7] IOCHRDY IRQ[3:7,10:12] DRQ[1:3] nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT KCLK MDAT MCLK
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t3 SAx SD<7:0> nIOW t1 t2
Figure 21.1 - IOW Timing for Port 92 IOW TIMING NAME t1 t2 t3 t4 t5 DESCRIPTION SAx Valid to nIOW Asserted SDATA Valid to nIOW Asserted nIOW Asserted to SAx Invalid nIOW Deasserted to DATA Invalid nIOW Deasserted to nIOW or nIOR Asserted MIN 40 0 10 0 100 TYP MAX UNITS ns ns ns ns ns
t4 t5
t1 V cc
t2 t3
A ll H o s t A ccesses
Figure 21.2 - Power-Up Timing NAME t1 t2 t3 DESCRIPTION Vcc Slew from 4.5V to 0V Vcc Slew from 0V to 4.5V All Host Accesses After Powerup (Note 21.1) MIN 300 100 125 500 TYP MAX UNITS s s s
Note 21.1 Internal write-protection period after Vcc passes 4.5 volts on power-up
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AEN SA[x], nCS t3 t2 nIOW SD[x] t1 t4
t10
t6 t5
DATA VALID t7
FINTR PINTR IBF t8 t9
Figure 21.3 - ISA Write
NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
DESCRIPTION SA[x], nCS and AEN valid to nIOW asserted nIOW asserted to nIOW deasserted nIOW asserted to SA[x], nCS invalid SD[x] Valid to nIOW deasserted SD[x] Hold from nIOW deasserted nIOW deasserted to nIOW asserted nIOW deasserted to FINTR deasserted (Note 21.2) nIOW deasserted to PINTER deasserted (Note 21.3) IBF (internal signal) asserted from nIOW deasserted nIOW deasserted to AEN invalid
MIN 10 80 10 45 25
TYP
MAX
0 55 260 40 10
UNITS ns ns ns ns ns ns ns ns ns ns
Note 21.2 FINTR refers to the IRQ used by the floppy disk. Note 21.3 PINTR refers to the IRQ used by the parallel port
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AEN SA[x], nCS t1 nIOR SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY FINTER PINTER PCOBF AUXOBF1 nIOR/nIOW t8 t9 t7 t4 DATA VALID t2 t3
t13
t6 t5
t10
t11 t12
Figure 21.4 - ISA Read
Table 21.1 - ISA Read Timing Parameters NAME t1 t2 t3 t4 t5 t6 t8 t8 t7 t9 t10 t11 t12 t13 DESCRIPTION SA[x], nCS and AEN valid to nIOR asserted nIOR asserted to nIOR deasserted nIOR asserted to SA[x], nCS invalid nIOR asserted to Data Valid Data Hold/float from nIOR deasserted nIOR deasserted nIOR asserted after nIOW deasserted nIOR/nIOR, nIOW/nIOW transfers from/to ECP FIFO Parallel Port setup to nIOR asserted nIOR asserted to PINTER deasserted nIOR deasserted to FINTER deasserted nIOR deasserted to PCOBF deasserted (Note 21.6, Note 21.8) nIOR deasserted to AUXOBF1 deasserted (Note 21.7, Note 21.8) nIOW deasserted to AEN invalid MIN 10 50 10 10 25 80 150 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
50 25
20 55 260 80 80 10
Note 21.4 FINTR refers to the IRQ used by the floppy disk. Note 21.5 PINTR refers to the IRQ used by the parallel port. Note 21.6 PCOBF is used for the Keyboard IRQ. Note 21.7 AUXOBF1 is used for the Mouse IRQ. Note 21.8 Applies only if deassertion is performed in hardware.
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t2 PCOBF t1 AUXOBF1 nWRT t3
IBF nRD
Figure 21.5 - Internal 8042 CPU Timing
NAME t1 t2 t3 Note 21.9
DESCRIPTION nWRT deasserted to AUXOBF1 asserted (Note 21.9, Note 21.10) nWRT deasserted to PCOBF asserted (Note 21.9, Note 21.11) nRD deasserted to IBF deasserted (Note 21.9) IBF, nWRT and nRD are internal signals.
MIN
TYP
MAX 40 40 40
UNITS ns ns ns
Note 21.10 PCOBF is used for the Keyboard IRQ. Note 21.11 AUXOBF1 is used for the Mouse IRQ.
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t1 t2 CLOCKI
Figure 21.6 - Input Clock Timing
t2
NAME t1 t2 t1 t2
DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32KHZ Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown)
MIN
TYP 70 35 31.25 16.53
MAX
UNITS ns ns s s ns
5
t4 RESET_DRV
Figure 21.7 - Reset Timing
NAME t4
DESCRIPTION RESET width (Note 21.12)
MIN 1.5
TYP
MAX
UNITS s
Note 21.12 The RESET width is dependent upon the processor clock. The RESET must be active while the clock is running and stable.
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t15 AEN t16 t3 t2 FDRQ, PDRQ nDACK t14 t11 t6 t5 t8 t1 t4 t12
nIOR or nIOW DATA (DO-D7)
t7 DATA VALID t13
t10 t9
TC
Figure 21.8 - DMA Timing (Single Transfer Mode) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 DESCRIPTION nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive MIN 0 TYP MAX 100 100 150 0 0 100 40 10 10 5 10 60 40 10 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
100
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t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK t12 t14 t11 t6 nIOR or nIOW t5 t8 t4
DATA (DO-D7)
t7 DATA VALID t13
t10 t9 DATA VALID
TC
Figure 21.9 - DMA Timing (Burst Transfer Mode)
NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16
DESCRIPTION nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive
MIN 0
TYP
MAX 100 100
150 0 0 100 40 10 10 5 10 60 40 10 60
100
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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t3 nDIR t4 nSTEP t1 t2
t5 nDS0-3 t6 nINDEX t7 nRDATA t8 nWDATA nIOW t9 t9
nDS0-1, MTR0-1
Figure 21.10 - Disk Drive Timing (At Mode Only)
NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 Notes:
DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTRO-1 from End of nIOW
MIN
TYP 4 24 96 132 20 2 40 .5 25
MAX
UNITS X* X* X* X* X* X* ns Y* ns
*X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz)
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nIOW t1
nRTSx, nDTRx IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW
t5
t6 t4
t3 IRQx nIOR nRIx
Figure 21.11 - Serial Port Timing
NAME t1 t2 t3 t4 t5 t6
DESCRIPTION nRTSx, nDTRx Delay from nIOW IRQx Active Delay from nCTSx, nDSRx, nDCDx IRQx Inactive Delay from nIOR (Leading Edge) IRQx Inactive Delay from nIOW (Trailing Edge) IRQx Inactive Delay from nIOW IRQx Active Delay from nRIx
MIN
TYP
10
MAX 200 100 120 125 100 100
UNITS ns ns ns ns ns ns
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PD0- PD7 t6 nIOW
nINIT, nSTROBE. nAUTOFD, SLCTIN nACK nPINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) t5 PINTR t2 t3 t2
t1
t4
t3
Figure 21.12 - Parallel Port Timing
NAME t1 t2 t3 t4 t5 t6 Note:
DESCRIPTION PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW PINTR Delay from nACK, nFAULT PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK nERROR Active to PINTR Active PD0 - PD7 Delay from IOW Active PINTR refers to the IRQ used by the parallel port.
MIN
TYP
200
MAX 100 60 300 105 105 100
UNITS ns ns ns ns ns ns
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t18 A0-A10 t9 SD<7:0> nIOW IOCHRDY t13 t22 t20 t1 PD<7:0> t14 t16 t3 t4 t17 t8 t10 t11 t12 t19
nWRITE
t2 t5
nDATAST nADDRSTB
t6 nWAIT PDIR t21
t15
t7
Figure 21.13 - EPP 1.9 Data or Address Write Cycle
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Table 21.2 - EPP 1.9 Data or Address Cycle Timing Parameters NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 DESCRIPTION nIOW Asserted to PDATA Valid nWAIT Asserted to nWRITE Change (Note 21.13) nWRITE to Command Asserted nWAIT Deasserted to Command Deasserted (Note 21.13) nWAIT Asserted to PDATA Invalid (Note 21.13) Time Out Command Deasserted to nWAIT Asserted SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted (Note 21.13) IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted nWAIT Asserted to Command Asserted (Note 21.13) Command Asserted to nWAIT Deasserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Asserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to nWRITE Asserted (Note 21.13) nWAIT Asserted to PDIR Low PDIR Low to nWRITE Asserted MIN 0 60 5 60 0 10 0 10 0 0 60 10 0 60 0 10 40 10 40 60 0 0 TYP MAX 50 185 35 190 12 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns
24 160 70 210 10
185
Note 21.13 nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec.
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t20 A0-A10 IOR SD<7:0> t8 t24 t23 PDIR t9 nWRITE t2 t25 PD<7:0> t28 t14 t26 t1 t5
PData bus driven by peripheral
t19 t13 t18 t10
t11 t12
t22
IOCHRDY
t27
t21
t17
t4
t16
DATASTB ADDRSTB
t3
t15 nWAIT
t7
t6
Figure 21.14 - EPP 1.9 Data or Address Read Cycle
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Table 21.3 - EPP 1.9 Data or Address Read Cycle Timing Parameters NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 DESCRIPTION PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted (Note 21.14) Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid PDATA Hi-Z to nWAIT Deasserted PDATA Valid to nWAIT Deasserted nIOR Asserted to IOCHRDY Asserted nWRITE Deasserted to nIOR Asserted (Note 21.15) nWAIT Deasserted to IOCHRDY Deasserted (Note 21.14) IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA Hi-Z (Hold Time) PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted Time Out nWAIT Deasserted to PDATA Driven (Note 21.14) nWAIT Deasserted to nWRITE Modified (Note 21.14, Note 21.15) SDATA Valid to IOCHRDY Deasserted (Note 21.16) Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDIR Set (Note 21.14) PDATA Hi-Z to PDIR Set nWAIT Asserted to PDATA Hi-Z (Note 21.14) PDIR Set to Command nWAIT Deasserted to PDIR Low (Note 21.14) nWRITE Deasserted to Command MIN 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 0 60 0 60 1 TYP MAX 30 50 180 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns
24 160 40 75 195 12 190 190 85 10 185 185 180 20 180
Note 21.14 nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. Note 21.15 When not executing a write cycle, EPP nWRITE is inactive high. Note 21.16 85 is true only if t7 = 0.
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t18 A0-A10 t9 SD<7:0> t17 t8 t6 t12 t10 t20 t19
nIOW
IOCHRDY t13
t11
t2
nWRITE
t1 PD<7:0> t16 t3 nDATAST nADDRSTB
t5
t4
nWAIT PDIR
t21
Figure 21.15 - EPP 1.7 Data or Address Write Cycle
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Table 21.4 - EPP 1.7 Data or Address Write Cycle Parameters NAME t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t16 t17 t18 t19 t20 t21 DESCRIPTION nIOW Asserted to PDATA Valid Command Deasserted to nWRITE Change nWRITE to Command nIOW Deasserted to Command Deasserted (Note 21.18) Command Deasserted to PDATA Invalid Time Out SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to nWAIT Deasserted MIN 0 0 5 50 10 10 0 0 10 0 10 40 10 100 45 0 TYP MAX 50 40 35 50 12 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns
24 40 50 35
Note 21.17 nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP Write. Note 21.18 The number is only valid if nWAIT is active when IOW goes active.
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t20 A0-A10 t15 t19 nIOR t13 SD<7:0> t8 t3 IOCHRDY t10 t12 t11 t22
nWRITE t5 PD<7:0> t23 t4
nDATASTB nADDRSTB
t2
t21 nWAIT
PDIR
Figure 21.16 - EPP 1.7 Data or Address Read Cycle Table 21.5 - EPP 1.7 Data or Address Read Cycle Parameters NAME t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 Note: DESCRIPTION nIOR Deasserted to Command Deasserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIOR Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA High-Z (Hold Time) PDATA Valid to SDATA Valid Time Out Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deasserted to nIOW or nIOR Asserted nIOR Asserted to Command Asserted MIN 0 0 0 TYP MAX 50 40 UNITS ns ns ns ns ns ns ns ns ns s ns ns ns ns ns
24 50 0 0 10 40 10 0 40 55 40 40 12
WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read.
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Chapter 22
ECP Parallel Port Timing
Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 22.2. ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 22.2. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has been accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 22.3.
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs.
t6 t3 PDATA nSTROBE t1 t2 t5
t4 BUSY
Figure 22.1 - Parallel Port FIFO Timing
NAME t1 t2 t3 t4 t5 t6
DESCRIPTION DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive (Note 22.1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 22.1)
MIN 600 600 450 680 80
TYP
MAX
500
UNITS ns ns ns ns ns ns
Note 22.1 The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
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t3 nAUTOFD t4 PDATA<7:0> t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8
Figure 22.2 - ECP Parallel Port Forward Timing
NAME t1 t2 t3 t4 t5 t6 t7 t8
DESCRIPTION nAUTOFD Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed (Note 22.2, Note 22.3) BUSY Deasserted to PDATA Changed (Note 22.2, Note 22.3) nSTROBE Deasserted to Busy Asserted nSTROBE Deasserted to Busy Deasserted BUSY Deasserted to nSTROBE Asserted (Note 22.2, Note 22.3) BUSY Asserted to nSTROBE Deasserted (Note 22.3)
MIN 0 0 80 80 0 0 80 80
TYP
MAX 60 60 180 180
UNITS ns ns ns ns ns ns ns ns
200 180
Note 22.2 Maximum value only applies if there is data in the FIFO waiting to be written out. Note 22.3 BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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t2 PDATA<7:0> t1 t5 nACK t4 nAUTOFD
Figure 22.3 - ECP Parallel Port Reverse Timing
t6
t3
t4
NAME t1 t2 t3 t4 t5 t6
DESCRIPTION PDATA Valid to nACK Asserted nAUTOFD Deasserted to PDATA Changed nACK Asserted to nAUTOFD Deasserted (Note 22.4, Note 22.5) nACK Deasserted to nAUTOFD Asserted (Note 22.5) nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted
MIN 0 0 80 80 0 0
TYP
MAX
200 200
UNITS ns ns ns ns ns ns
Note 22.4 Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nAUTOFD low. Note 22.5 nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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DATA
0 t2 t1
1 t2
0
1
0
0
1
1
0
1
1
t1
IRRX n IRRX
Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud
min 1.4 1.4 1.4 1.4 1.4 1.4 1.4
typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416
max 2.71 3.69 5.53 11.07 22.13 44.27 88.55
units s s s s s s s s s s s s s s
Notes: 1. Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a minimum of 1.41s. 2. IRRX: L5, CRF1 Bit 0: 1 = RCV active low nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default)
Figure 22.4 - IrDA Receive Timing
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DATA
0 t2 t1
1
0
1
0
0
1
1
0
1
1
t2
t1
IRTX n IRTX
Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud
min 1.41 1.41 1.41 1.41 1.41 1.41 1.41
typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416
max 2.71 3.69 5.53 11.07 22.13 44.27 88.55
units s s s s s s s s s s s s s s
Notes: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. 2. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default) nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high
Figure 22.5 - IrDA Transmit Timing
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D A TA
0 t1
1 t2
0
1
0
0
1
1
0
1
1
IR R X n IR R X
t3 M IR R X t5 nM IR R X
t4
t6
P aram eter t1 t2 t3 t4 t5 t6 M odulated O utput B it Tim e O ff B it Tim e M odulated O utput "O n" M odulated O utput "O ff" M odulated O utput "O n" M odulated O utput "O ff"
m in
typ
m ax
units s s
0.8 0.8 0.8 0.8
1 1 1 1
1.2 1.2 1.2 1.2
s s s s
N otes: 1. IR R X : L5, C R F1 B it 0: 1 = R C V active low nIR R X : L5, C R F1 B it 0: 0 = R C V active high (default) M IR R X , nM IR R X are the m odulated outputs
Figure 22.6 - Amplitude Shift Keyed IR Receive Timing
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Enhanced Super I/O Controller with Fast IR Datasheet
DATA
0 t1
1 t2
0
1
0
0
1
1
0
1
1
IRTX n
t3 MIRTX t5 nMIRTX
t4
t6
Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "Off"
min
typ
max
units s s
0.8 0.8 0.8 0.8
1 1 1 1
1.2 1.2 1.2 1.2
s s s s
Notes: 1. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default) nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high MIRTX, nMIRTX are the modulated outputs
Figure 22.7 - Amplitude Shift Keyed IR Transmit Timing
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Enhanced Super I/O Controller with Fast IR Datasheet
Chapter 23 Package Outlines
D D1
E
E1
e
W
A
A2
T D /T E
H 0 .10 -C0 A1 L L1
D IM A A1 A2 D D1 E E1 H L L1 e 0 W T D (1 ) T E (1 ) T D (2 ) T E (2 )
M IN 2 .8 0 0 .1 2 .5 7 2 3 .4 1 9 .9 1 7 .4 1 3 .9
MAX 3 .1 5 0 .4 5 2 .8 7 2 4 .1 5 2 0 .1 1 8 .1 5 1 4 .1
M IN .1 1 0 .0 0 4 .1 0 1 .9 2 1 .7 8 3 .6 8 5 .5 4 7
M AX .1 2 4 .0 1 8 .1 1 3 .9 5 1 .7 9 1 .7 1 5 .5 5 5
N o te s: 1 ) C o p la n a rity is 0 .1 0 0 m m (.0 0 4 ") m a xim u m . 2 ) T o le ra n ce o n th e p o sitio n o f th e le a d s is 0 .2 0 0 m m (.0 0 8 ") m a xim u m . 3 ) P a cka g e b o d y d im e n sio n s D 1 a n d E 1 d o n o t in clu d e th e m o ld p ro tru sio n . M a xim u m m o ld p ro tru sio n is 0 .2 5 m m (.0 1 0 "). 4 ) D im e n sio n s T D a n d TE a re im p o rta n t fo r te stin g b y ro b o tic h a n d le r. O n ly a b o ve co m b in a tio n s o f (1 ) o r (2 ) a re a cce p ta b le . 5 ) C o n tro llin g d im e n sio n : m illim e te r. D im e n sio n s in in ch e s fo r re fe re n ce o n ly a n d n o t n e ce ssa rily a ccu ra te .
0 .1 0 .2 0 .6 5 0 .9 5 1 .8 2 .6 0 .6 5 B S C 0 12 .4 .2 2 1 .8 1 5 .8 2 2 .2 1 1 6 .2 7 2 2 .2 1 6 .2 2 2 .7 6 1 6 .8 2
.0 0 4 .0 0 8 .0 2 6 .0 3 7 .1 0 2 .0 7 1 .0 2 5 6 B S C 0 12 .0 0 8 .0 1 6 .8 5 8 .6 2 2 .8 7 4 .6 4 1 .8 7 4 .6 3 8 .8 9 6 .6 6 2
Figure 23.1 - 100 Pin QFP Package Outline and Parameters
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Figure 23.2 - 100 Pin TQFP Package Outline, 14X14X1.4 Body, 2 MM Footprint Table 23.1 - 100 Pin TQFP Package Parameters A A1 A2 D D1 E E1 H L L1 e W R1 R2 ccc MIN ~ 0.05 1.35 15.80 13.90 15.80 13.90 0.09 0.45 ~ 0o 0.17 0.08 0.08 ~ NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.50 Basic ~ 0.22 ~ ~ ~ MAX 1.60 0.15 1.45 16.20 14.10 16.20 14.10 0.20 0.75 ~ 7o 0.27 ~ 0.20 0.08 REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
Notes: 1. Controlling Unit: millimeter. 2. Tolerance on the position of the leads is 0.04 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated.
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